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參數(shù)資料
| 型號(hào)： | DS1372U+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 2/12頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC BINARY COUNTER 32-BIT 8-USOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 類型： | 二進(jìn)制計(jì)數(shù)器 |
| 特點(diǎn)： | 警報(bào)器，方波輸出，監(jiān)視計(jì)時(shí)器 |
| 時(shí)間格式： | 二進(jìn)制 |
| 數(shù)據(jù)格式： | 二進(jìn)制 |
| 接口： | I²C，2 線串口 |
| 電源電壓： | 2.4 V ~ 5.5 V |
| 電壓 - 電源，電池： | 1.3 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-uMAX |
| 包裝： | 帶卷 (TR) |
DS1372
Accordingly, the following bus conditions have been
defined:
Bus not busy: Both data and clock lines remain
high.
Start data transfer: A change in the state of the
data line from high to low, while the clock line is high,
defines a START condition.
Stop data transfer: A change in the state of the data
line from low to high, while the clock line is high,
defines a STOP condition.
Data valid: The state of the data line represents
valid data when, after a START condition, the data
line is stable for the duration of the high period of the
clock signal. The data on the line must be changed
during the low period of the clock signal. There is
one clock pulse per bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number
of data bytes transferred between the START and
the STOP conditions is not limited, and is determined
by the master device. The information is transferred
byte-wise and each receiver acknowledges with a
ninth bit.
Acknowledge: Each receiving device, when
addressed, is obliged to generate an acknowledge
after the reception of each byte. The master device
must generate an extra clock pulse, which is associ-
ated with this acknowledge bit.
A device that acknowledges must pull down the SDA
line during the acknowledge clock pulse in such a
way that the SDA line is stable low during the high
period of the acknowledge-related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the
last byte that has been clocked out of the slave. In
this case, the slave must leave the data line high to
enable the master to generate the STOP condition.
Timeout: To avoid an unintended I2C interface time-
out, SCL should not be held low longer than 25ms.
The I2C interface is in the reset state and can
receive a new START condition when SCL is held
low for at least 35ms. When the part detects this con-
dition, SDA is released and allowed to float. For the
timeout function to work, the oscillator must be
enabled and running.
Depending upon the state of the R/W bit, two types of
data transfer are possible:
1) Data transfer from a master transmitter to a
slave receiver. The first byte transmitted by the
master is the slave address. Next follows a num-
ber of data bytes. The slave returns an acknowl-
edge bit after each received byte. Data is
transferred with the most significant bit (MSB) first.
2) Data transfer from a slave transmitter to a
master receiver. The first byte (the slave
address) is transmitted by the master. The slave
then returns an acknowledge bit. Next follows a
number of data bytes transmitted by the slave to
the master. The master returns an acknowledge
bit after all received bytes other than the last byte.
At the end of the last received byte, a not
acknowledge is returned.
The master device generates all the serial clock
pulses and the START and STOP conditions. A
transfer is ended with a STOP condition or with a
repeated START condition. Since a repeated
START condition is also the beginning of the next
serial transfer, the bus will not be released. Data
is transferred with the most significant bit (MSB)
first.
The DS1372 can operate in the following two modes:
1) Slave receiver mode (DS1372 write mode): Serial
data and clock are received through SDA and SCL.
After each byte is received an acknowledge bit is
transmitted. START and STOP conditions are recog-
nized as the beginning and end of a serial transfer.
Address recognition is performed by hardware after
reception of the slave address and direction bit (see
Figure 6). The slave address byte is the first byte
received after the master generates the START con-
dition. The slave address byte contains the 7-bit
DS1372 address, which is 110100 and AD0. Each
slave address is followed by the direction bit (R/W),
which is zero for a write. The bit position signified by
A is compared to the value on the AD0 input pin.
After receiving and decoding the slave address
byte, the device outputs an acknowledge on the
SDA line. After the device acknowledges the slave
address and write bit, the master transmits a register
address to the device. This sets the register pointer
on the device. After setting the register address, the
master then transmits each byte of data with the
DS1372 acknowledging each byte received. The
master generates a STOP condition to terminate the
data write.
10
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