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參數(shù)資料
| 型號(hào)： | DS1372U+T&R |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 10/12頁 |
| 文件大小： | 0K |
| 描述： | IC BINARY COUNTER 32-BIT 8-USOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 3,000 |
| 類型： | 二進(jìn)制計(jì)數(shù)器 |
| 特點(diǎn)： | 警報(bào)器，方波輸出，監(jiān)視計(jì)時(shí)器 |
| 時(shí)間格式： | 二進(jìn)制 |
| 數(shù)據(jù)格式： | 二進(jìn)制 |
| 接口： | I²C，2 線串口 |
| 電源電壓： | 2.4 V ~ 5.5 V |
| 電壓 - 電源，電池： | 1.3 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-TSSOP，8-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-uMAX |
| 包裝： | 帶卷 (TR) |
Control Register (07h)
Bit 7: Enable Oscillator (EOSC). When set to logic 0,
the oscillator is started. When set to logic 1, the oscilla-
tor is stopped. This bit is clear (logic 0) when power is
first applied.
Bit 6: Alarm Counter Enable (ACE). When set to logic
1, the alarm counter is enabled. If alarm counter seed
register has a nonzero value, the counter runs and sets
the AF bit to 1 when the counter reaches 0. When set to
logic 0, the alarm counter is disabled, and the counter
can be used as RAM. This bit is clear (logic 0) when
power is first applied.
Bit 3: Interrupt Control (INTCN). This bit controls the
SQW/INT signal. When the INTCN bit is set to logic 0, a
square wave is output on the SQW/INT pin whose fre-
quency is defined by bits RS2 and RS1, according to
Table 2. The oscillator must also be enabled for the
square wave to be output. When the INTCN bit is set to
logic 1, this permits the AF bit in the Status Register to
assert SQW/INT (provided that ACE and AIE are also
enabled) whenever AF = 1. If ACE = 1, the alarm flag is
always set on an alarm condition, regardless of the
state of the INTCN bit. The INTCN bit is set to logic 1
when power is first applied.
Bits 2 and 1: Rate Select (RS[2:1]). These bits control
the frequency of the square-wave output when the
square wave has been enabled. Table 2 shows the
square-wave frequencies that can be selected with the
RS bits. These bits are both set (logic 1) when power is
first applied.
Bit 0: Alarm Interrupt Enable (AIE). When set to a
logic 1, this bit permits the alarm flag (AF) to assert
SQW/INT (when INTCN = 1). The AIE bit is disabled
(logic 0) when power is first applied.
Table 2. Square-Wave/Interrupt Output
Frequencies
Note: When interrupt operation is enabled, the SQW/INT out-
put is the inverse of the AF bit.
Bit #
7
6
5
4
3
2
1
0
Name
EOSC
ACE
0
INTCN
RS2
RS1
AIE
Reset
0
1
0
Control Register (07h)
DS1372
_______________________________________________________________________________________
7
Special Purpose Registers
The DS1372 has two additional registers that control
the alarm counter and interrupts: Control Register (07h)
and Status Register (08h).
INTCN
ACE
AIE
RS2
RS1
SQW/
INT
OUTPUT
0
X
0
1Hz
0
X
0
1
4.096kHz
0
X
1
0
8.192kHz
0
X
1
32.768kHz
1
X
Interrupt
I2C, 32-Bit, Binary Counter Clock with 64-Bit ID
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|---|---|
| DS1374 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:I2C, 32-Bit Binary Counter Watchdog RTC with Trickle Charger and Reset Input/Output |
| DS1374_10 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:I2C, 32-Bit Binary Counter Watchdog RTC with Trickle Charger and Reset Input/Output |
| DS1374C-18 | 功能描述:實(shí)時(shí)時(shí)鐘 I2C 32-Bit Binary Counter Watchdog RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時(shí)間格式:HH:MM:SS RTC 存儲(chǔ)容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
| DS1374C-18- | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:I2C, 32-Bit Binary Counter Watchdog RTC with Trickle Charger and Reset Input/Output |
| DS1374C-18# | 功能描述:實(shí)時(shí)時(shí)鐘 I2C 32-Bit Binary Counter Watchdog RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 總線接口:I2C 日期格式:DW:DM:M:Y 時(shí)間格式:HH:MM:SS RTC 存儲(chǔ)容量:64 B 電源電壓-最大:5.5 V 電源電壓-最小:1.8 V 最大工作溫度:+ 85 C 最小工作溫度: 安裝風(fēng)格:Through Hole 封裝 / 箱體:PDIP-8 封裝:Tube |
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