參數(shù)資料
型號(hào): DS1318E+
廠商: Maxim Integrated Products
文件頁數(shù): 2/15頁
文件大?。?/td> 0K
描述: IC COUNTER ELAPSED TIME 24-TSSOP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 62
類型: 耗用時(shí)間計(jì)數(shù)器
特點(diǎn): 警報(bào)器,方波輸出
時(shí)間格式: 二進(jìn)制
數(shù)據(jù)格式: 二進(jìn)制
接口: 并聯(lián)
電源電壓: 3 V ~ 3.6 V
電壓 - 電源,電池: 1.6 V ~ 3.7 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 24-TSSOP
包裝: 管件
產(chǎn)品目錄頁面: 1433 (CN2011-ZH PDF)
DS1318
Counter Operation
The binary time information is obtained by reading the
appropriate register bytes. Registers 02h through 05h
contain the time in seconds from an arbitrary reference
time determined by the user. Registers 00h and 01h
contain the fractional seconds count. A buffered copy
of the clock registers (A0–A5), updated every 244s,
allows the user to read and write the registers while the
internal registers continue to increment. However, it is
possible to read or write inconsistent data, or for a write
to corrupt the current buffered read copy, if an update
occurs during the read or write. Several methods may
be used to ensure that the data is accurate.
The clock registers can be read, with the least-signifi-
cant byte (LSB) being read once at the beginning and
again after the other registers have been read (i.e.,
A2–A5, A2). If the LSB register data has changed, the
registers should be re-read until the LSB register data
matches. If the subseconds0 register is used, the user
never has more than 244s to read all the registers
before a mismatch occurs. In addition, if the routine
used to read the registers takes approximately 1.95ms
to read the registers, it is possible that the
subseconds0 register could roll over to the same value
as previously read.
Other methods use the TE and UIP bits to synchronize
accessing the clock registers to ensure that the data are
valid. These methods are discussed in later sections.
Alarm
To use the alarm function, the user writes registers 06h
through 09h with a time in seconds. When the current
time in seconds becomes equal to the alarm value, the
ALMF bit in the status register (0Ch) is set to 1. If the
AIE bit in control register A is set to 1 by the user, then
the IRQ pin is driven low when the ALMF bit is set to 1.
The alarm and IRQ output operate when the device is
running from either supply.
Periodic Flag
Writing a non-zero value into the periodic flag rate-
select bits in control register B enables the periodic
flag operation. The periodic flag is set to logic 1 when
the internal counter reaches the selected value. Writing
the PF bit to 0 resets the periodic flag. If the flag is not
reset, it remains high. Once the PF bit is set, the inter-
nal counter continues counting, and attempts to set the
PF bit again when the count again matches the select-
ed rate value. Clearing the PF bit has no effect on the
internal counter. If the PIE bit in control register A is set
to 1, the IRQ output goes low when the PF bit is set.
The periodic flag and IRQ output operates when the
device is running from either supply.
Note that writing to the subseconds or seconds regis-
ters affects the setting of the PF flag and IRQ output.
The square-wave output uses a separate prescaler and
is not affected by changes to the subseconds or sec-
onds bits.
Parallel-Interface Elapsed Time Counter
10
____________________________________________________________________
Table 3. Address Map
Note: Unless otherwise specified, the state of the registers is not defined when power is first applied.
ADDRESS
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
FUNCTION
RANGE
00h
SS3
SS2
SS1
SS0
0
SQWS
Subseconds0
00–F0h
01h
SS11
SS10
SS9
SS8
SS7
SS6
SS5
SS4
Subseconds1
00–FFh
02h
S7
S6
S5
S4
S3
S2
S1
S0
Seconds0
00–FFh
03h
S15
S14
S13
S12
S11
S10
S9
S8
Seconds1
00–FFh
04h
S23
S22
S21
S20
S19
S18
S17
S16
Seconds2
00–FFh
05h
S31
S30
S29
S28
S27
S26
S25
S24
Seconds3
00–FFh
06h
ALM7
ALM6
ALM5
ALM4
ALM3
ALM2
ALM1
ALM0
Alarm0
00–FFh
07h
ALM15
ALM14
ALM13
ALM12
ALM11
ALM10
ALM9
ALM8
Alarm1
00–FFh
08h
ALM23
ALM22
ALM21
ALM20
ALM19
ALM18
ALM17
ALM16
Alarm2
00–FFh
09h
ALM31
ALM30
ALM29
ALM28
ALM27
ALM26
ALM25
ALM24
Alarm3
00–FFh
0Ah
TE
ENOSC
CCFG1
CCFG0
EPOL
SQWE
PIE
AIE
ControlA
00–FFh
0Bh
PRS3
PRS2
PRS1
PRS0
SRS3
SRS2
SRS1
SRS0
ControlB
00–FFh
0Ch
OSF
UIP
0
PF
ALMF
Status
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