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| 型號(hào)： | DP83848CVV/NOPB |
| 廠商： | National Semiconductor |
| 文件頁(yè)數(shù)： | 53/86頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX ETHERNET PHYTER 48-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | PHYTER® Family |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 類型： | 收發(fā)器 |
| 驅(qū)動(dòng)器/接收器數(shù)： | 1/1 |
| 規(guī)程： | 以太網(wǎng) |
| 電源電壓： | 3 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁(yè)面： | 1276 (CN2011-ZH PDF) |
| 配用： | DP83848C-POE-EK-ND - BOARD EVALUATION DP83848C DP83848C-MAU-EK-ND - BOARD EVALUATION DP83848C |
| 其它名稱： | *DP83848CVV *DP83848CVV/NOPB DP83848CVV DP83848CVVNOPB DP83848CVVNOPB-ND DP83848CVVNOPBTR DP83848CVVNOPBTR-ND |
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56
D
P
83
84
8C
7.2.7 RMII and Bypass Register (RBR)
This register configures the RMII Mode of operation. When RMII mode is disabled, the RMII functionality is bypassed.
7.2.8 LED Direct Control Register (LEDCR)
This register provides the ability to directly control any or all LED outputs. It does not provide read access to LEDs.
Table 27. RMII and Bypass Register (RBR), addresses 0x17
Bit
Bit Name
Default
Description
15:6
RESERVED
0, RO
RESERVED: Writes ignored, read as 0.
5
RMII_MODE
Strap, RW
Reduced MII Mode:
0 = Standard MII Mode
1 = Reduced MII Mode
4
RMII_REV1_0
0, RW
Reduce MII Revision 1.0:
0 = (RMII revision 1.2) CRS_DV will toggle at the end of a packet
to indicate deassertion of CRS.
1 = (RMII revision 1.0) CRS_DV will remain asserted until final data
is transferred. CRS_DV will not toggle at the end of a packet.
3
RX_OVF_STS
0, RO
RX FIFO Over Flow Status:
0 = Normal
1 = Overflow detected
2
RX_UNF_STS
0, RO
RX FIFO Under Flow Status:
0 = Normal
1 = Underflow detected
1:0
ELAST_BUF[1:0]
01, RW
Receive Elasticity Buffer. This field controls the Receive Elastic-
ity Buffer which allows for frequency variation tolerance between
the 50MHz RMII clock and the recovered data. The following val-
ues indicate the tolerance in bits for a single packet. The minimum
setting allows for standard Ethernet frame sizes at +/-50ppm accu-
racy for both RMII and Receive clocks. For greater frequency tol-
erance the packet lengths may be scaled (i.e. for +/-100ppm, the
packet lengths need to be divided by 2).
00 = 14 bit tolerance (up to 16800 byte packets)
01 = 2 bit tolerance (up to 2400 byte packets)
10 = 6 bit tolerance (up to 7200 byte packets)
11 = 10 bit tolerance (up to 12000 byte packets)
Table 28. LED Direct Control Register (LEDCR), address 0x18
Bit
Bit Name
Default
Description
15:6
RESERVED
0, RO
RESERVED: Writes ignored, read as 0.
5
DRV_SPDLED
0, RW
1 = Drive value of SPDLED bit onto LED_SPD output
0 = Normal operation
4
DRV_LNKLED
0, RW
1 = Drive value of LNKLED bit onto LED_LNK output
0 = Normal operation
3
DRV_ACTLED
0, RW
1 = Drive value of ACTLED bit onto LED_ACT/COL output
0 = Normal operation
2
SPDLED
0, RW
Value to force on LED_SPD output
1
LNKLED
0, RW
Value to force on LED_LNK output
0
ACTLED
0, RW
Value to force on LED_ACT/COL output
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DP83848CVVX | 制造商:Texas Instruments 功能描述:PHY 1-CH 10Mbps/100Mbps 48-Pin LQFP T/R |
| DP83848CVVX/NOPB | 功能描述:以太網(wǎng) IC PHYTER COMMERCIAL TEMP SGL PORT RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| DP83848EVV/NOPB | 功能描述:以太網(wǎng) IC RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| DP83848EVVX/NOPB | 功能描述:以太網(wǎng) IC 10/100 ETHERNET PHY RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| DP83848H | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:DP83848H PHYTER㈢ Mini - Extreme Single 10/100 Ethernet |
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