參數(shù)資料
型號(hào)： DP83848CVV/NOPB
廠商： National Semiconductor
文件頁(yè)數(shù)： 41/86頁(yè)
文件大?。?/td> 0K
描述： IC TXRX ETHERNET PHYTER 48-LQFP
產(chǎn)品培訓(xùn)模塊： PHYTER® Family
標(biāo)準(zhǔn)包裝： 250
類型： 收發(fā)器
驅(qū)動(dòng)器/接收器數(shù)： 1/1
規(guī)程： 以太網(wǎng)
電源電壓： 3 V ~ 3.6 V
安裝類型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP（7x7）
包裝： 托盤
產(chǎn)品目錄頁(yè)面： 1276 (CN2011-ZH PDF)
配用： DP83848C-POE-EK-ND - BOARD EVALUATION DP83848C
DP83848C-MAU-EK-ND - BOARD EVALUATION DP83848C
其它名稱： *DP83848CVV
*DP83848CVV/NOPB
DP83848CVV
DP83848CVVNOPB
DP83848CVVNOPB-ND
DP83848CVVNOPBTR
DP83848CVVNOPBTR-ND
45
www.national.com
DP
83
84
8
C
The PHY Identifier Registers #1 and #2 together form a unique identifier for the DP83848C. The Identifier consists of a
concatenation of the Organizationally Unique Identifier (OUI), the vendor's model number and the model revision num-
ber. A PHY may return a value of zero in each of the 32 bits of the PHY Identifier if desired. The PHY Identifier is intended
to support network management. National's IEEE assigned OUI is 080017h.
7.1.3 PHY Identifier Register #1 (PHYIDR1)
7.1.4 PHY Identifier Register #2 (PHYIDR2)
7.1.5 Auto-Negotiation Advertisement Register (ANAR)
This register contains the advertised abilities of this device as they will be transmitted to its link partner during Auto-Nego-
tiation.
Table 14. PHY Identifier Register #1 (PHYIDR1), address 0x02
Bit
Bit Name
Default
Description
15:0
OUI_MSB
<0010 0000 0000
0000>, RO/P
OUI Most Significant Bits: Bits 3 to 18 of the OUI (080017h) are
stored in bits 15 to 0 of this register. The most significant two bits
of the OUI are ignored (the IEEE standard refers to these as bits 1
and 2).
Table 15. PHY Identifier Register #2 (PHYIDR2), address 0x03
Bit
Bit Name
Default
Description
15:10
OUI_LSB
<0101 11>, RO/P OUI Least Significant Bits:
Bits 19 to 24 of the OUI (080017h) are mapped from bits 15 to 10
of this register respectively.
9:4
VNDR_MDL
<00 1001>, RO/P Vendor Model Number:
The six bits of vendor model number are mapped from bits 9 to 4
(most significant bit to bit 9).
3:0
MDL_REV
<0000>, RO/P
Model Revision Number:
Four bits of the vendor model revision number are mapped from
bits 3 to 0 (most significant bit to bit 3). This field will be incremented
for all major device changes.
Table 16. Negotiation Advertisement Register (ANAR), address 0x04
Bit
Bit Name
Default
Description
15
NP
0, RW
Next Page Indication:
0 = Next Page Transfer not desired.
1 = Next Page Transfer desired.
14
RESERVED
0, RO/P
RESERVED by IEEE: Writes ignored, Read as 0.
13
RF
0, RW
Remote Fault:
1 = Advertises that this device has detected a Remote Fault.
0 = No Remote Fault detected.
12
RESERVED
0, RW
RESERVED for Future IEEE use: Write as 0, Read as 0
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