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參數(shù)資料
| 型號： | DC941A |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 9/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD DELTA SIGMA ADC LTC2482 |
| 軟件下載： | QuikEval System |
| 設(shè)計(jì)資源： | DC941A Design File DC941A Schematic |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Easy Drive™, QuikEval™ |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 6.8 |
| 數(shù)據(jù)接口： | MICROWIRE?，串行，SPI? |
| 工作溫度： | 0°C ~ 70°C |
| 已用 IC / 零件： | LTC2482 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | LTC2482IDD#TRPBF-ND - IC ADC 16BIT 10-DFN LTC2482CDD#TRPBF-ND - IC ADC 16BIT 10-DFN LTC2482IDD#PBF-ND - IC ADC 16BIT 10-DFN LTC2482CDD#PBF-ND - IC ADC 16BIT 10-DFN |
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LTC2482
17
2482fc
APPLICATIONS INFORMATION
External Serial Clock, 2-Wire I/O
This timing mode utilizes a 2-wire serial I/O interface. The
conversion result is shifted out of the device by an externally
generated serial clock (SCK) signal (see Figure 6). CS
may be permanently tied to ground, simplifying the user
interface or transmission over an isolation barrier.
The external serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
typically 4ms after VCC exceeds approximately 2V. The level
applied to SCK at this time determines if SCK is internal or
external. SCK must be driven low prior to the end of POR
in order to enter the external serial clock timing mode.
Since CS is tied low, the end-of-conversion (EOC) can be
continuously monitored at the SDO pin during the con-
vert and sleep states. EOC may be used as an interrupt
to an external controller indicating the conversion result
is ready. EOC = 1 while the conversion is in progress and
EOC = 0 once the conversion ends. On the falling edge of
EOC, the conversion result is loaded into an internal static
shift register. The output data is shifted out of the SDO pin
on each falling edge of SCK. EOC can be latched on the
rst rising edge of SCK. On the 24th falling edge of SCK,
SDO goes high (EOC = 1) indicating a new conversion has
begun. In applications where the processor generates 32
clock cycles, or to remain compatible with higher resolution
converters, the LTC2482’s digital interface will ignore extra
clock edges seen during the next conversion period after
the 24th and outputs “1” for the extra clock cycles.
Internal Serial Clock, Single Cycle Operation
This timing mode uses an internal serial clock to shift out
the conversion result and a CS signal to monitor and control
the state of the conversion cycle (see Figure 7).
In order to select the internal serial clock timing mode, the
serial clock pin (SCK) must be oating (Hi-Z) or pulled high
prior to the falling edge of CS. The device will not enter the
internal serial clock mode if SCK is driven low on the falling
edge of CS. An internal weak pull-up resistor is active on
the SCK pin during the falling edge of CS; therefore, the
internal serial clock timing mode is automatically selected
if SCK is not externally driven.
The serial data output pin (SDO) is Hi-Z as long as CS is
high. At any time during the conversion cycle, CS may be
pulled low in order to monitor the state of the converter.
Once CS is pulled low, SCK goes low and EOC is output
to the SDO pin. EOC = 1 while a conversion is in progress
and EOC = 0 if the device is in the sleep state.
EOC
BIT 23
SDO
SCK
(EXTERNAL)
CS
MSB
SIG
LSB
BIT 4
BIT 19
BIT 18
BIT 17
BIT 16
BIT 20
BIT 21
BIT 22
DATA OUTPUT
CONVERSION
2482 F06
CONVERSION
VCC
fO
VREF
IN+
IN–
SCK
SDO
CS
GND
210
INT/EXT CLOCK
3
4
5
9
7
8,1
6
REFERENCE
VOLTAGE
0.1V TO VCC
ANALOG
INPUT
1μF
2.7V TO 5.5V
LTC2482
2-WIRE
SPI INTERFACE
Figure 6. External Serial Clock, CS = 0 Operation
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