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參數(shù)資料
| 型號： | DC941A |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 14/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD DELTA SIGMA ADC LTC2482 |
| 軟件下載： | QuikEval System |
| 設(shè)計資源： | DC941A Design File DC941A Schematic |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Easy Drive™, QuikEval™ |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 6.8 |
| 數(shù)據(jù)接口： | MICROWIRE?，串行，SPI? |
| 工作溫度： | 0°C ~ 70°C |
| 已用 IC / 零件： | LTC2482 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | LTC2482IDD#TRPBF-ND - IC ADC 16BIT 10-DFN LTC2482CDD#TRPBF-ND - IC ADC 16BIT 10-DFN LTC2482IDD#PBF-ND - IC ADC 16BIT 10-DFN LTC2482CDD#PBF-ND - IC ADC 16BIT 10-DFN |
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LTC2482
21
2482fc
APPLICATIONS INFORMATION
An alternate solution is to reduce the edge rate of the control
signals. It should be noted that using very slow edges will
increase the converter power supply current during the
transition time. The differential input architecture reduces
the converter’s sensitivity to ground currents.
Particular attention must be given to the connection of
the fO signal when the LTC2482 is used with an external
conversion clock. This clock is active during the conver-
sion time and the normal mode rejection provided by the
internal digital lter is not very high at this frequency. A
normal mode signal of this frequency at the converter
reference terminals can result in DC gain and INL errors.
A normal mode signal of this frequency at the converter
input terminals can result in a DC offset error. Such pertur-
bations can occur due to asymmetric capacitive coupling
between the fO signal trace and the converter input and/or
reference connection traces. An immediate solution is to
maintain maximum possible separation between the fO
signal trace and the input/reference signals. When the fO
signal is parallel terminated near the converter, substantial
AC current is owing in the loop formed by the fO con-
nection trace, the termination and the ground return path.
Thus, perturbation signals may be inductively coupled into
the converter input and/or reference. In this situation, the
user must reduce to a minimum the loop area for the fO
signal as well as the loop area for the differential input
and reference connections. Even when f0 is not driven,
other nearby signals pose similar EMI threats which will
be minimized by following good layout practices.
Driving the Input and Reference
The input and reference pins of the LTC2482 converter
are directly connected to a network of sampling capaci-
tors. Depending upon the relation between the differential
input voltage and the differential reference voltage, these
capacitors are switching between these four pins transfer-
ring small amounts of charge in the process. A simplied
equivalent circuit is shown in Figure 10.
For a simple approximation, the source impedance RS
driving an analog input pin (IN+, IN–, VREF+ or GND) can
be considered to form, together with RSW and CEQ (see
Figure 10), a rst order passive network with a time
constant
τ = (RS + RSW) CEQ. The converter is able to
sample the input signal with better than 1ppm accuracy
if the sampling period is at least 14 times greater than the
input circuit time constant
τ. The sampling process on
the four input analog pins is quasi-independent so each
time constant should be considered by itself and, under
worst-case circumstances, the errors may add.
VREF
+
VIN
+
VCC
RSW (TYP)
10k
ILEAK
VCC
ILEAK
VCC
RSW (TYP)
10k
CEQ
12pF
(TYP)
RSW (TYP)
10k
ILEAK
IIN
+
VIN
–
IIN
–
IREF
+
IREF
–
2482 F10
ILEAK
VCC
LEAK
SWITCHING FREQUENCY
fSW = 123kHz INTERNAL OSCILLATOR
fSW = 0.4 fEOSC EXTERNAL OSCILLATOR
GND
RSW (TYP)
10k
Figure 10. LTC2482 Equivalent Analog Input Current
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