參數(shù)資料
型號(hào)： DC941A
廠商： Linear Technology
文件頁(yè)數(shù)： 10/32頁(yè)
文件大?。?/td> 0K
描述： BOARD DELTA SIGMA ADC LTC2482
軟件下載： QuikEval System
設(shè)計(jì)資源： DC941A Design File
DC941A Schematic
標(biāo)準(zhǔn)包裝： 1
系列： Easy Drive™, QuikEval™
ADC 的數(shù)量： 1
位數(shù)： 16
采樣率（每秒）： 6.8
數(shù)據(jù)接口： MICROWIRE?，串行，SPI?
工作溫度： 0°C ~ 70°C
已用 IC / 零件： LTC2482
已供物品： 板
相關(guān)產(chǎn)品： LTC2482IDD#TRPBF-ND - IC ADC 16BIT 10-DFN
LTC2482CDD#TRPBF-ND - IC ADC 16BIT 10-DFN
LTC2482IDD#PBF-ND - IC ADC 16BIT 10-DFN
LTC2482CDD#PBF-ND - IC ADC 16BIT 10-DFN
LTC2482
18
2482fc
APPLICATIONS INFORMATION
When testing EOC, if the conversion is complete (EOC = 0),
the device will exit the low power mode during the EOC test.
In order to allow the device to return to the low power sleep
state, CS must be pulled high before the rst rising edge of
SCK. In the internal SCK timing mode, SCK goes high and the
device begins outputting data at time tEOCtest after the falling
edge of CS (if EOC = 0) or tEOCtest after EOC goes low (if CS
is low during the falling edge of EOC). The value of tEOCtest is
12μs if the device is using its internal oscillator. If fO is driven
by an external oscillator of frequency fEOSC, then tEOCtest is
3.6/fEOSC in seconds. If CS is pulled high before time tEOCtest,
the device returns to the sleep state and the conversion result
is held in the internal static shift register.
If CS remains low longer than tEOCtest, the rst rising edge
of SCK will occur and the conversion result is serially shifted
out of the SDO pin. The data I/O cycle concludes after the
24th rising edge. The output data is shifted out of the SDO
pin on each falling edge of SCK. The internally generated
serial clock is output to the SCK pin. This signal may be
used to shift the conversion result into external circuitry.
EOC can be latched on the rst rising edge of SCK and the
last bit of the conversion result on the 24th rising edge of
SCK. After the 24th rising edge, SDO goes high (EOC = 1),
SCK stays high and a new conversion starts.
Typically, CS remains low during the data output state.
However, the data output state may be aborted by pulling
CS high anytime between the rst and 24th rising edge of
SCK (see Figure 8). On the rising edge of CS, the device
aborts the data output state and immediately initiates a new
conversion. This is useful for systems not requiring all 24
bits of output data, aborting an invalid conversion cycle,
or synchronizing the start of a conversion. If CS is pulled
high while the converter is driving SCK low, the internal
pull-up is not available to restore SCK to a logic high state.
This will cause the device to exit the internal serial clock
mode on the next falling edge of CS. This can be avoided
by adding an external 10k pull-up resistor to the SCK pin
or by never pulling CS high when SCK is low.
Whenever SCK is low, the LTC2482’s internal pull-up at pin
SCK is disabled. Normally, SCK is not externally driven if
the device is in the internal SCK timing mode. However,
certain applications may require an external driver on SCK.
If this driver goes Hi-Z after outputting a low signal, the
LTC2482’s internal pull-up remains disabled. Hence, SCK
remains low. On the next falling edge of CS, the device is
switched to the external SCK timing mode. By adding an
external 10k pull-up resistor to SCK, this pin goes high once
the external driver goes Hi-Z. On the next CS falling edge,
the device will remain in the internal SCK timing mode.
SDO
SCK
(INTERNAL)
CS
MSB
SIG
BIT 0
LSB
BIT 4
TEST EOC
BIT 19
BIT 18
BIT 17
BIT 16
BIT 20
BIT 21
BIT 22
EOC
BIT 23
SLEEP
DATA OUTPUT
CONVERSION
2482 F07
<tEOCtest
Hi-Z
TEST EOC
VCC
fO
VREF
IN+
IN–
SCK
SDO
CS
GND
210
INT/EXT CLOCK
3
4
5
9
10k
VCC
7
8,1
6
REFERENCE
VOLTAGE
0.1V TO VCC
ANALOG
INPUT
1μF
2.7V TO 5.5V
LTC2482
3-WIRE
SPI INTERFACE
Figure 7. Internal Serial Clock, Single Cycle Operation
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