參數(shù)資料
型號： DC745A
廠商： Linear Technology
文件頁數(shù)： 9/28頁
文件大小： 0K
描述： BOARD DELTA SIGMA ADC LTC2433-1
軟件下載： QuikEval System
設(shè)計(jì)資源： DC745A Design File
DC745A Schematic
標(biāo)準(zhǔn)包裝： 1
系列： QuikEval™
ADC 的數(shù)量： 2
位數(shù)： 16
采樣率（每秒）： 6.8
數(shù)據(jù)接口： MICROWIRE?，串行，SPI?
工作溫度： 0°C ~ 70°C
已用 IC / 零件： LTC2433-1
已供物品： 板
相關(guān)產(chǎn)品： LTC2433-1IMS#PBF-ND - IC ADC DIFF 16BIT 3WIRE 10-MSOP
LTC2433-1CMS#TRPBF-ND - IC ADC DIFF 16BIT 3WIRE 10-MSOP
LTC2433-1IMS#TRPBF-ND - IC ADC DIFF 16BIT 3WIRE 10-MSOP
LTC2433-1CMS#PBF-ND - IC ADC DIFF 16BIT 3WIRE 10-MSOP
LTC2433-1IMS#TR-ND - IC CONV A/D 16BIT DIFF 10-MSOP
LTC2433-1CMS#TR-ND - IC CONV A/D 16BIT DIFF 10-MSOP
LTC2433-1IMS-ND - IC CONV A/D 16BIT DIFF 10-MSOP
LTC2433-1CMS-ND - IC ADC DIFF 16BIT 3WIRE 10-MSOP
LTC2433-1
17
24331fa
disabled. Hence, SCK remains LOW. On the next falling
edge of CS, the device is switched to the external SCK
timing mode. By adding an external 10k pull-up resistor to
SCK, this pin goes HIGH once the external driver goes
Hi-Z. On the next CS falling edge, the device will remain in
the internal SCK timing mode.
A similar situation may occur during the sleep state when
CS is pulsed HIGH-LOW-HIGH in order to test the
conversion status. If the device is in the sleep state (EOC
= 0), SCK will go LOW. Once CS goes HIGH (within the time
period defined above as tEOCtest), the internal pull-up is
activated. For a heavy capacitive load on the SCK pin, the
internal pull-up may not be adequate to return SCK to a
HIGH level before CS goes low again. This is not a concern
under normal conditions where CS remains LOW after
detecting EOC = 0. This situation is easily overcome by
adding an external 10k pull-up resistor to the SCK pin.
Internal Serial Clock, 2-Wire I/O,
Continuous Conversion
This timing mode uses a 2-wire, all output (SCK and SDO)
interface. The conversion result is shifted out of the device
by an internally generated serial clock (SCK) signal, see
Figure 11. CS may be permanently tied to ground, simpli-
fying the user interface or isolation barrier.
The internal serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
approximately 1ms after VCC exceeds 2V. An internal weak
pull-up is active during the POR cycle; therefore, the
internal serial clock timing mode is automatically selected
if SCK is not externally driven LOW (if SCK is loaded such
that the internal pull-up cannot pull the pin HIGH, the
external SCK mode will be selected).
Figure 10. Internal Serial Clock, Reduced Data Output Length
SDO
SCK
(INTERNAL)
CS
>tEOCtest
MSB
SIG
“O”
BIT 2
TEST EOC
BIT 14
BIT 13
BIT 15
BIT 16
BIT 17
EOC
BIT 18
EOC
BIT 0
DATA OUTPUT
Hi-Z
DATA
OUTPUT
CONVERSION
SLEEP
24331 F10
<tEOCtest
VCC
10k
TEST EOC
(OPTIONAL)
TEST EOC
SLEEP
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/SIMULTANEOUS
50Hz/60Hz REJECTION
VCC
FO
REF+
REF–
SCK
IN+
IN–
SDO
GND
CS
110
2
3
9
4
5
8
6
7
REFERENCE
VOLTAGE
0.1V TO VCC
ANALOG INPUT RANGE
–0.5VREF TO 0.5VREF
1
F
2.7V TO 5.5V
LTC2433-1
3-WIRE
SPI INTERFACE
APPLICATIO S I FOR ATIO
WU
UU
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