- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄17066 > DC745A (Linear Technology)BOARD DELTA SIGMA ADC LTC2433-1 PDF資料下載
參數(shù)資料
| 型號(hào)： | DC745A |
| 廠商： | Linear Technology |
| 文件頁(yè)數(shù)： | 27/28頁(yè) |
| 文件大小： | 0K |
| 描述： | BOARD DELTA SIGMA ADC LTC2433-1 |
| 軟件下載： | QuikEval System |
| 設(shè)計(jì)資源： | DC745A Design File DC745A Schematic |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | QuikEval™ |
| ADC 的數(shù)量： | 2 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 6.8 |
| 數(shù)據(jù)接口： | MICROWIRE?，串行，SPI? |
| 工作溫度： | 0°C ~ 70°C |
| 已用 IC / 零件： | LTC2433-1 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | LTC2433-1IMS#PBF-ND - IC ADC DIFF 16BIT 3WIRE 10-MSOP LTC2433-1CMS#TRPBF-ND - IC ADC DIFF 16BIT 3WIRE 10-MSOP LTC2433-1IMS#TRPBF-ND - IC ADC DIFF 16BIT 3WIRE 10-MSOP LTC2433-1CMS#PBF-ND - IC ADC DIFF 16BIT 3WIRE 10-MSOP LTC2433-1IMS#TR-ND - IC CONV A/D 16BIT DIFF 10-MSOP LTC2433-1CMS#TR-ND - IC CONV A/D 16BIT DIFF 10-MSOP LTC2433-1IMS-ND - IC CONV A/D 16BIT DIFF 10-MSOP LTC2433-1CMS-ND - IC ADC DIFF 16BIT 3WIRE 10-MSOP |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)當(dāng)前第27頁(yè)第28頁(yè)
LTC2433-1
8
24331fa
CONVERTER OPERATION
Converter Operation Cycle
The LTC2433-1 is a low power,
Σ ADC with differential
input/reference and an easy-to-use 3-wire serial interface
(see Figure 1). Its operation is made up of three states.
The converter operating cycle begins with the conversion,
followed by the low power sleep state and ends with the
data output (see Figure 2). The 3-wire interface consists
of serial data output (SDO), serial clock (SCK) and chip
select (CS).
Initially, the LTC2433-1 performs a conversion. Once the
conversion is complete, the device enters the sleep state.
The part remains in the sleep state as long as CS is HIGH.
While in this sleep state, power consumption is reduced by
nearly two orders of magnitude. The conversion result is
held indefinitely in a static shift register while the converter
is in the sleep state.
Once CS is pulled LOW, the device exits the low power
mode and enters the data output state. If CS is pulled HIGH
before the first rising edge of SCK, the device returns to the
low power sleep mode and the conversion result is still
held in the internal static shift register. If CS remains LOW
after the first rising edge of SCK, the device begins
outputting the conversion result. Taking CS high at this
point will terminate the data output state and start a new
conversion. There is no latency in the conversion result.
The data output corresponds to the conversion just per-
formed. This result is shifted out on the serial data out pin
(SDO) under the control of the serial clock (SCK). Data is
updated on the falling edge of SCK allowing the user to
reliably latch data on the rising edge of SCK (see Figure 3).
The data output state is concluded once 19 bits are read
out of the ADC or when CS is brought HIGH. The device
automatically initiates a new conversion and the cycle
repeats. In order to maintain compatibility with 24-/32-bit
data transfers, it is possible to clock the LTC2433-1 with
additional serial clock pulses. This results in additional
data bits which are logic HIGH.
Through timing control of the CS and SCK pins, the
LTC2433-1 offers several flexible modes of operation
(internal or external SCK and free-running conversion
modes). These various modes do not require program-
ming configuration registers; moreover, they do not dis-
turb the cyclic operation described above. These modes of
operation are described in detail in the Serial Interface
Timing Modes section.
Conversion Clock
A major advantage the delta-sigma converter offers over
conventional type converters is an on-chip digital filter
(commonly implemented as a Sinc or Comb filter). For
high resolution, low frequency applications, this filter is
typically designed to reject line frequencies of 50Hz and
60Hz plus their harmonics. The filter rejection perfor-
mance is directly related to the accuracy of the converter
system clock. The LTC2433-1 incorporates a highly accu-
rate on-chip oscillator. This eliminates the need for exter-
nal frequency setting components such as crystals or
oscillators. Clocked by the on-chip oscillator, the
LTC2433-1 achieves a minimum of 87dB rejection over
the range 49Hz to 61.2Hz.
Ease of Use
The LTC2433-1 data output has no latency, filter settling
delay or redundant data associated with the conversion
cycle. There is a one-to-one correspondence between the
conversion and the output data. Therefore, multiplexing
multiple analog voltages is easy.
Figure 2. LTC2433-1 State Transition Diagram
CONVERT
SLEEP
DATA OUTPUT
24331 F02
TRUE
FALSE
CS = LOW
AND
SCK
APPLICATIO S I FOR ATIO
WU
UU
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| RMM08DRXS | CONN EDGECARD 16POS DIP .156 SLD |
| SC75B-100 | INDUCTOR SMD 10UH 2.30A 2.52MHZ |
| RBM11DRAH | CONN EDGECARD 22POS R/A .156 SLD |
| CI160808-12NJ | INDUCTOR 12NH 300MA SMD |
| 0210490986 | CABLE JUMPER 1.25MM .030M 29POS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DC746A | 功能描述:BOARD DELTA SIGMA ADC LTC2412 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估板 - 模數(shù)轉(zhuǎn)換器 (ADC) 系列:QuikEval™ 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- ADC 的數(shù)量:1 位數(shù):12 采樣率（每秒）:94.4k 數(shù)據(jù)接口:USB 輸入范圍:±VREF/2 在以下條件下的電源（標(biāo)準(zhǔn)）:- 工作溫度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，軟件 |
| DC74HC259 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:High Speed CMOS Logic 8-Bit Addressable Latch |
| DC-750 | 制造商:Bivar 功能描述:CARD GUIDE DEEP 7.5" 0.08" BK |
| DC-750-102 | 制造商:Bivar 功能描述:CARD GUIDE DEEP 7.5" 0.102" BK |
| DC-750-102-CI | 制造商:Bivar 功能描述:CARD GUIDE INSERT 7.5" 0.102" BK |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。