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參數(shù)資料
| 型號： | DC571A |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 45/48頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD DELTA SIGMA ADC LTC2418 |
| 軟件下載： | QuikEval System |
| 設(shè)計資源： | DC571A Design File DC571A Schematic |
| 標準包裝： | 1 |
| 系列： | QuikEval™ |
| ADC 的數(shù)量： | 1 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 7.5 |
| 數(shù)據(jù)接口： | MICROWIRE?，串行，SPI? |
| 工作溫度： | 0°C ~ 70°C |
| 已用 IC / 零件： | LTC2418 |
| 已供物品： | 板 |
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LTC2414/LTC2418
6
241418fa
Note 1: Absolute Maximum Ratings are those values beyond which the
life of the device may be impaired.
Note 2: All voltage values are with respect to GND.
Note 3: VCC = 2.7V to 5.5V unless otherwise specified.
VREF = REF
+ – REF–, VREFCM = (REF+ + REF–)/2; VIN = IN+ – IN–,
VINCM = (IN+ + IN–)/2, IN+ and IN– are defined as the selected positive
and negative input respectively.
Note 4: FO pin tied to GND or to VCC or to external conversion clock
source with fEOSC = 153600Hz unless otherwise specified.
Note 5: Guaranteed by design, not subject to test.
Note 6: Integral nonlinearity is defined as the deviation of a code from
a straight line passing through the actual endpoints of the transfer
curve. The deviation is measured from the center of the quantization
band.
Note 7: FO = 0V (internal oscillator) or fEOSC = 153600Hz ±2%
(external oscillator).
Note 8: FO = VCC (internal oscillator) or fEOSC = 128000Hz ±2%
(external oscillator).
Note 9: The converter is in external SCK mode of operation such that
the SCK pin is used as digital input. The frequency of the clock signal
driving SCK during the data output is fESCK and is expressed in kHz.
Note 10: The converter is in internal SCK mode of operation such that
the SCK pin is used as digital output. In this mode of operation the
SCK pin has a total equivalent load capacitance CLOAD = 20pF.
Note 11: The external oscillator is connected to the FO pin. The external
oscillator frequency, fEOSC, is expressed in kHz.
Note 12: The converter uses the internal oscillator.
FO = 0V or FO = VCC.
Note 13: The output noise includes the contribution of the internal
calibration operations.
Note 14: Guaranteed by design and test correlation.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
t1
CS
↓ to SDO Low
●
0
200
ns
t2
CS
↑ to SDO High Z
●
0
200
ns
t3
CS
↓ to SCK ↓
(Note 10)
●
0
200
ns
t4
CS
↓ to SCK ↑
(Note 9)
●
50
ns
tKQMAX
SCK
↓ to SDO Valid
●
220
ns
tKQMIN
SDO Hold After SCK
↓
(Note 5)
●
15
ns
t5
SCK Set-Up Before CS
↓
●
50
ns
t6
SCK Hold After CS
↓
●
50
ns
t7
SDI Setup Before SCK
↑
(Note 5)
●
100
ns
t8
SDI Hold After SCK
↑
(Note 5)
●
100
ns
The
● denotes specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 3)
TI I G CHARACTERISTICS
U
W
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