RSOURCE () 0 100 200 300 400 500 600 700 800 900 100" />
參數(shù)資料
型號(hào)： DC571A
廠商： Linear Technology
文件頁(yè)數(shù)： 21/48頁(yè)
文件大小： 0K
描述： BOARD DELTA SIGMA ADC LTC2418
軟件下載： QuikEval System
設(shè)計(jì)資源： DC571A Design File
DC571A Schematic
標(biāo)準(zhǔn)包裝： 1
系列： QuikEval™
ADC 的數(shù)量： 1
位數(shù)： 24
采樣率（每秒）： 7.5
數(shù)據(jù)接口： MICROWIRE?，串行，SPI?
工作溫度： 0°C ~ 70°C
已用 IC / 零件： LTC2418
已供物品： 板
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LTC2414/LTC2418
28
241418fa
RSOURCE ()
0 100 200 300 400 500 600 700 800 900 1000
+FS
ERROR
(ppm
OF
V
REF
)
2414/18 F15
300
240
180
120
60
0
VCC = 5V
REF+ = 5V
REF – = GND
IN+ = 3.75V
IN– = 1.25V
FO = GND
TA = 25°C
CIN = 0.01F
CIN = 0.1F
CIN = 1F, 10F
RSOURCE ()
0 100 200 300 400 500 600 700 800 900 1000
–
FS
ERROR
(ppm
OF
V
REF
)
2414/18 F16
0
–60
–120
–180
–240
–300
VCC = 5V
REF+ = 5V
REF – = GND
IN+ = 1.25V
IN– = 3.75V
FO = GND
TA = 25°C
CIN = 0.01F
CIN = 0.1F
CIN = 1F, 10F
VINCM (V)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
OFFSET
ERROR
(ppm
OF
V
REF
)
2414/18 F17
120
100
80
60
40
20
0
–20
–40
–60
–80
–100
–120
FO = GND
TA = 25°C
RSOURCEIN– = 500
CIN = 10F
VCC = 5V
REF+ = 5V
REF – = GND
IN+ = IN– = VINCM
A:
RIN = +400
B:
RIN = +200
C:
RIN = +100
D:
RIN = 0
E:
RIN = –100
F:
RIN = –200
G:
RIN = –400
A
B
C
D
E
F
G
Figure 15. +FS Error vs RSOURCE at IN+ or IN– (Large CIN)
Figure 16. –FS Error vs RSOURCE at IN
+ or IN– (Large CIN)
Figure 17. Offset Error vs Common Mode Voltage
(VINCM = IN+ = IN–) and Input Source Resistance Imbalance
(
RIN = RSOURCEIN+ – RSOURCEIN–) for Large CIN Values (CIN ≥ 1F)
APPLICATIO S I FOR ATIO
WU
UU
1.78 10–6 fEOSCppm. Figure 17 shows the typical offset
error due to input common mode voltage for various
values of source resistance imbalance between the IN+
and IN– pins when large CIN values are used.
If possible, it is desirable to operate with the input signal
common mode voltage very close to the reference signal
common mode voltage as is the case in the ratiometric
measurement of a symmetric bridge. This configuration
eliminates the offset error caused by mismatched source
impedances.
The magnitude of the dynamic input current depends upon
the size of the very stable internal sampling capacitors and
upon the accuracy of the converter sampling clock. The
accuracy of the internal clock over the entire temperature
and power supply range is typical better than 0.5%. Such
a specification can also be easily achieved by an external
clock. When relatively stable resistors (50ppm/
°C) are
used for the external source impedance seen by IN+ and
IN–, the expected drift of the dynamic current, offset and
gain errors will be insignificant (about 1% of their respec-
tive values over the entire temperature and voltage range).
Even for the most stringent applications, a one-time
calibration operation may be sufficient.
In addition to the input sampling charge, the input ESD
protection diodes have a temperature dependent leakage
current. This current, nominally 1nA (
±10nA max), results
in a small offset shift. A 100
source resistance will create
a 0.1
V typical and 1V maximum offset voltage.
Reference Current
In a similar fashion, the LTC2414/LTC2418 samples the
differential reference pins REF+ and REF– transferring
small amount of charge to and from the external driving
circuits thus producing a dynamic reference current. This
current does not change the converter offset, but it may
degrade the gain and INL performance. The effect of this
current can be analyzed in the same two distinct situa-
tions.
For relatively small values of the external reference capaci-
tors (CREF < 0.01F), the voltage on the sampling capacitor
settles almost completely and relatively large values for
the source impedance result in only small errors. Such
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