values for CREF will deteriorate the converter offset and
參數(shù)資料
型號： DC571A
廠商： Linear Technology
文件頁數(shù)： 22/48頁
文件大?。?/td> 0K
描述： BOARD DELTA SIGMA ADC LTC2418
軟件下載： QuikEval System
設(shè)計資源： DC571A Design File
DC571A Schematic
標準包裝： 1
系列： QuikEval™
ADC 的數(shù)量： 1
位數(shù)： 24
采樣率（每秒）： 7.5
數(shù)據(jù)接口： MICROWIRE?，串行，SPI?
工作溫度： 0°C ~ 70°C
已用 IC / 零件： LTC2418
已供物品： 板
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LTC2414/LTC2418
29
241418fa
values for CREF will deteriorate the converter offset and
gain performance without significant benefits of reference
filtering and the user is advised to avoid them.
Larger values of reference capacitors (CREF > 0.01F) may
be required as reference filters in certain configurations.
Such capacitors will average the reference sampling charge
and the external source resistance will see a quasi con-
stant reference differential impedance. When FO = LOW
(internal oscillator and 60Hz notch), the typical differential
reference resistance is 1.3M
which will generate a gain
error of approximately 0.38ppm for each ohm of source
resistance driving REF+ or REF–. When FO = HIGH (internal
oscillator and 50Hz notch), the typical differential refer-
ence resistance is 1.56M
whichwillgenerateagainerror
APPLICATIO S I FOR ATIO
WU
UU
RSOURCE ()
1
10
100
1k
10k
100k
+FS
ERROR
(ppm
OF
V
REF
)
2414/18 F18
0
–10
–20
–30
–40
–50
VCC = 5V
REF+ = 5V
REF – = GND
IN+ = 3.75V
IN – = 1.25V
FO = GND
TA = 25°C
CREF = 0.01F
CREF = 0.001F
CREF = 100pF
CREF = 0pF
RSOURCE ()
1
10
100
1k
10k
100k
–
FS
ERROR
(ppm
OF
V
REF
)
2414/18 F19
50
40
30
20
10
0
VCC = 5V
REF+ = 5V
REF – = GND
IN+ = 1.25V
IN – = 3.75V
FO = GND
TA = 25°C
CREF = 0.01F
CREF = 0.001F
CREF = 100pF
CREF = 0pF
RSOURCE ()
0 100 200 300 400 500 600 700 800 900 1000
+
FS
ERROR
(ppm
OF
V
REF
)
2414/18 F20
0
–90
–180
–270
–360
–450
VCC = 5V
REF+ = 5V
REF– = GND
IN+ = 3.75V
IN – = 1.25V
FO = GND
TA = 25°C
CREF = 0.01F
CREF = 0.1F
CREF = 1F, 10F
RSOURCE ()
0 100 200 300 400 500 600 700 800 900 1000
–
FS
ERROR
(ppm
OF
V
REF
)
2414/18 F21
450
360
270
180
90
0
VCC = 5V
REF+ = 5V
REF– = GND
IN+ = 1.25V
IN – = 3.75V
FO = GND
TA = 25°C
CREF = 0.01F
CREF = 0.1F
CREF = 1F, 10F
Figure 18. +FS Error vs RSOURCE at REF
+ or REF– (Small CIN)
Figure 19. –FS Error vs RSOURCE at REF
+ or REF– (Small CIN)
Figure 20. +FS Error vs RSOURCE at REF+ and REF– (Large CREF)
Figure 21. –FS Error vs RSOURCE at REF+ and REF– (Large CREF)
of approximately 0.32ppm for each ohm of source resis-
tance driving REF+ or REF–. When FO is driven by an
external oscillator with a frequency fEOSC (external conver-
sion clock operation), the typical differential reference
resistance is 0.20 1012/fEOSC and each ohm of source
resistance driving REF+ or REF– will result in
2.47 10–6 fEOSCppm gain error. The effect of the source
resistance on the two reference pins is additive with
respect to this gain error. The typical +FS and –FS errors
for various combinations of source resistance seen by the
REF+ and REF– pins and external capacitance CREF con-
nected to these pins are shown in Figures 18, 19, 20
and 21.
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