參數(shù)資料
型號： DC570A
廠商： Linear Technology
文件頁數(shù)： 23/28頁
文件大?。?/td> 0K
描述： BOARD DELTA SIGMA ADC LTC2440
軟件下載： QuikEval System
設(shè)計資源： DC570A Design File
DC570A Schematic
標(biāo)準(zhǔn)包裝： 1
系列： QuikEval™
ADC 的數(shù)量： 2
位數(shù)： 24
采樣率（每秒）： 3.5k
數(shù)據(jù)接口： MICROWIRE?，串行，SPI?
工作溫度： 0°C ~ 70°C
已用 IC / 零件： LTC2440
已供物品： 板
相關(guān)產(chǎn)品： LTC2440CGN#TRPBF-ND - IC ADC DIFFER 24-BIT HS 16-SSOP
LTC2440IGN#TRPBF-ND - IC ADC DIFFER 24-BIT HS 16-SSOP
LTC2440IGN#PBF-ND - IC ADC DIFFER 24-BIT HS 16-SSOP
LTC2440CGN#PBF-ND - IC ADC DIFFER 24-BIT HS 16-SSOP
LTC2440IGN#TR-ND - IC CONV A/D 24-BIT DIFF 16-SSOP
LTC2440CGN#TR-ND - IC CONV A/D 24-BIT DIFF 16-SSOP
LTC2440IGN-ND - IC ADC DIFFER 24-BIT HS 16-SSOP
LTC2440CGN-ND - IC ADC DIFFER 24-BIT HS 16-SSOP
LTC2440
4
2440fd
↑
POWER REQUIREMENTS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may
cause permanent damage to the device. Exposure to any Absolute Maximum
Rating condition for extended periods may affect device reliability and lifetime.
Note 2: All voltage values are with respect to GND.
Note 3: VCC = 4.5 to 5.5V unless otherwise specied.
VREF = REF+ – REF–, VREFCM = (REF+ + REF–)/2;
VIN = IN+ – IN–, VINCM = (IN+ + IN–)/2.
Note 4: fO pin tied to GND or to external conversion clock source with
fEOSC = 10MHz unless otherwise specied.
Note 5: Guaranteed by design, not subject to test.
Note 6: Integral nonlinearity is dened as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VCC
Supply Voltage
l
4.5
5.5
V
ICC
Supply Current
Conversion Mode
Sleep Mode
CS = 0V (Note 7)
CS = VCC (Note 7)
l
8
11
30
mA
μA
The
l denotes the specications which apply over the full operating temperature
range, otherwise specications are at TA = 25°C. (Note 3)
TIMING CHARACTERISTICS The l denotes the specications which apply over the full operating temperature
range, otherwise specications are at TA = 25°C. (Note 3)
Note 7: The converter uses the internal oscillator.
Note 8: The converter is in external SCK mode of operation such that the
SCK pin is used as a digital input. The frequency of the clock signal driving
SCK during the data output is fESCK and is expressed in Hz.
Note 9: The converter is in internal SCK mode of operation such that the
SCK pin is used as a digital output. In this mode of operation, the SCK pin
has a total equivalent load capacitance of CLOAD = 20pF.
Note 10: The external oscillator is connected to the fO pin. The external
oscillator frequency, fEOSC, is expressed in kHz.
Note 11: The converter uses the internal oscillator. fO = 0V.
Note 12: Guaranteed by design and test correlation.
Note 13: There is an internal reset that adds an additional 1μs (typical) to
the conversion time.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
fEOSC
External Oscillator Frequency Range
l
0.1
20
MHz
tHEO
External Oscillator High Period
l
25
10000
ns
tLEO
External Oscillator Low Period
l
25
10000
ns
tCONV
Conversion Time
OSR = 256 (SDI = 0)
OSR = 32768 (SDI = 1)
External Oscillator (Note 10, 13)
l
0.99
126
1.13
145
40 OSR + 170
fEOSC(kHz)
1.33
170
ms
fISCK
Internal SCK Frequency
Internal Oscillator (Note 9)
External Oscillator (Notes 9, 10)
l
0.8
0.9
fEOSC /10
1
DISCK
Internal SCK Duty Cycle
(Note 9)
l
45
55
%
fESCK
External SCK Frequency Range
(Note 8)
l
20
MHz
tLESCK
External SCK Low Period
(Note 8)
l
25
ns
tHESCK
External SCK High Period
(Note 8)
l
25
ns
tDOUT_ISCK
Internal SCK 32-Bit Data Output Time
Internal Oscillator (Notes 9, 11)
External Oscillator (Notes 9, 10)
l
30.9
35.3
320/fEOSC
41.6
μs
s
tDOUT_ESCK
External SCK 32-Bit Data Output Time
(Note 8)
l
32/fESCK
s
t1
CS to SDO Low Z
(Note 12)
l
025
ns
t2
CS
↑ to SDO High Z
(Note 12)
l
025
ns
t3
CS to SCK
(Note 9)
l
5μs
t4
CS to SCK
↑
(Notes 8, 12)
l
25
ns
tKQMAX
SCK to SDO Valid
l
25
ns
tKQMIN
SDO Hold After SCK
(Note 5)
l
15
ns
t5
SCK Set-Up Before CS
l
50
ns
t7
SDI Setup Before SCK
↑
(Note 5)
l
10
ns
t8
SDI Hold After SCK
↑
(Note 5)
l
10
ns
↑
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