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參數(shù)資料
| 型號(hào)： | DC570A |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 10/28頁 |
| 文件大小： | 0K |
| 描述： | BOARD DELTA SIGMA ADC LTC2440 |
| 軟件下載： | QuikEval System |
| 設(shè)計(jì)資源： | DC570A Design File DC570A Schematic |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | QuikEval™ |
| ADC 的數(shù)量： | 2 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 3.5k |
| 數(shù)據(jù)接口： | MICROWIRE?，串行，SPI? |
| 工作溫度： | 0°C ~ 70°C |
| 已用 IC / 零件： | LTC2440 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | LTC2440CGN#TRPBF-ND - IC ADC DIFFER 24-BIT HS 16-SSOP LTC2440IGN#TRPBF-ND - IC ADC DIFFER 24-BIT HS 16-SSOP LTC2440IGN#PBF-ND - IC ADC DIFFER 24-BIT HS 16-SSOP LTC2440CGN#PBF-ND - IC ADC DIFFER 24-BIT HS 16-SSOP LTC2440IGN#TR-ND - IC CONV A/D 24-BIT DIFF 16-SSOP LTC2440CGN#TR-ND - IC CONV A/D 24-BIT DIFF 16-SSOP LTC2440IGN-ND - IC ADC DIFFER 24-BIT HS 16-SSOP LTC2440CGN-ND - IC ADC DIFFER 24-BIT HS 16-SSOP |
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LTC2440
18
2440fd
APPLICATIONS INFORMATION
on this rst rising edge of SCK and concludes after the
32nd rising edge. Data is shifted out the SDO pin on each
falling edge of SCK. The internally generated serial clock
is output to the SCK pin. This signal may be used to shift
the conversion result into external circuitry. EOC can be
latched on the rst rising edge of SCK and the last bit of
the conversion result on the 32nd rising edge of SCK.
After the 32nd rising edge, SDO goes HIGH (EOC = 1),
SCK stays HIGH and a new conversion starts.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pull-
ing CS HIGH anytime between the rst and 32nd rising
edge of SCK, see Figure 9. In order to properly select the
OSR for the conversion following a data abort, ve SCK
rising edges must be seen prior to performing a data out
abort (pulling CS HIGH). If CS is pulled high prior to the
fth SCK falling edge, the OSR selected depends on the
number of SCK signals seen prior to data abort, where
subsequent nonaborted conversion cycles return to the
programmed OSR. On the rising edge of CS, the device
aborts the data output state and immediately initiates a
Figure 9. Internal Serial Clock, Reduced Data Output Length
new conversion. This is useful for systems not requiring
all 32-bits of output data, aborting an invalid conversion
cycle, or synchronizing the start of a conversion.
Internal Serial Clock, 2-Wire I/O,
Continuous Conversion
This timing mode uses a 2-wire, all output (SCK and SDO)
interface. The conversion result is shifted out of the device
by an internally generated serial clock (SCK) signal, see
Figure 10. CS may be permanently tied to ground, sim-
plifying the user interface or isolation barrier. The internal
serial clock mode is selected by tying EXT HIGH.
During the conversion, the SCK and the serial data output
pin (SDO) are HIGH (EOC = 1) and BUSY = 1. Once the
conversion is complete, SCK, BUSY and SDO go LOW (EOC
= 0) indicating the conversion has nished and the device
has entered the low power sleep state. The part remains in
the sleep state a minimum amount of time (≈500ns) then
immediately begins outputting data. The data output cycle
begins on the rst rising edge of SCK and ends after the
32nd rising edge. Data is shifted out the SDO pin on each
SDO
BUSY
SCK
(INTERNAL)
CS
>tEOCtest
MSB
SIG
BIT 8
TEST EOC
BIT 27
BIT 26
BIT 28
BIT 29
BIT 30
EOC
BIT 31
EOC
BIT 0
SLEEP
DATA OUTPUT
Hi-Z
5
1
Hi-Z
DATA OUTPUT
CONVERSION
SLEEP
2440 F09
<tEOCtest
TEST EOC
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
VCC
fO
REF+
REF–
SCK
BUSY
IN+
IN–
SDO
GND
CS
EXT
2
14
3
4
13
5
6
12
1, 8, 9, 16
11
10
15
SDI
VCC
7
REFERENCE VOLTAGE
0.1V TO VCC
ANALOG INPUT RANGE
–0.5VREF TO 0.5VREF
1μF
4.5V TO 5.5V
LTC2440
3-WIRE
SPI INTERFACE
200nV NOISE, 50/60Hz REJECTION
10-SPEED/RESOLUTION PROGRAMMABLE
2μV NOISE, 880Hz OUTPUT RATE
VCC
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