VDD = 2.7V to 3.3V
參數(shù)資料
型號(hào): DC1110A
廠商: Linear Technology
文件頁(yè)數(shù): 18/22頁(yè)
文件大?。?/td> 0K
描述: BOARD DAC LTC2751-16
軟件下載: QuikEval System
設(shè)計(jì)資源: DC1110A Design File
DC1110A Schematic
標(biāo)準(zhǔn)包裝: 1
系列: QuikEval™, SoftSpan™
DAC 的數(shù)量: 1
位數(shù): 16
數(shù)據(jù)接口: 并聯(lián)
設(shè)置時(shí)間: 2µs
DAC 型: 電流
工作溫度: 0°C ~ 70°C
已供物品:
已用 IC / 零件: LTC2751-16
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LTC2751
5
2751fa
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VDD = 2.7V to 3.3V
Write and Update Timing
t1
I/O Valid to WR Rising Edge Set-Up
l
18
ns
t2
I/O Valid to WR Rising Edge Hold
l
18
ns
t3
WR Pulse Width
l
30
ns
t4
UPD Pulse Width
l
30
ns
t5
UPD Falling Edge to WR Falling Edge
No Data Shoot-Through
l
0
ns
t6
WR Rising Edge to UPD Rising Edge
(Note 10)
l
0
ns
t7
D/S Valid to WR Falling Edge Set-Up Time
l
18
ns
t8
WR Rising Edge to D/S Valid Hold Time
l
18
ns
Readback Timing
t13
WR Rising Edge to Read Rising Edge
l
18
ns
t14
Read Falling Edge to WR Falling Edge
(Note 10)
l
40
ns
t15
Read Rising Edge to I/O Propagation Delay
CL = 10pF
l
40
ns
t17
UPD Valid to I/O Propagation Delay
CL = 10pF
l
40
ns
t18
D/S Valid to Read Rising Edge
(Note 10)
l
18
ns
t19
Read Rising Edge to UPD Rising Edge
No Update
l
9
ns
t20
UPD Falling Edge to Read Falling Edge
No Update
l
9
ns
t22
READ Falling Edge to UPD Rising Edge
(Note 10)
l
18
ns
t23
I/O Bus Hi-Z to Read Rising Edge
(Note 10)
l
0
ns
t24
Read Falling Edge to I/O Bus Active
(Note 10)
l
40
ns
CLR Timing
t25
CLR Pulse Width Low
l
30
ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Continuous operation above the specified maximum operating
junction temperature may impair device reliability.
Note 3: Because of the proprietary SoftSpan switching architecture, the
measured resistance looking into each of the specified pins is constant for
all output ranges if the IOUT1 and IOUT2 pins are held at ground.
Note 4: R1 is measured from RIN to RCOM; R2 is measured from REF to
RCOM.
Note 5: Using LT1469 with CFEEDBACK = 15pF. A ±0.0015% settling time
of 1.7μs can be achieved by optimizing the time constant on an individual
TiMing characTerisTics V
DD = 5V, VREF = 5V unless otherwise specified. The l denotes specifications that
apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
basis. See Application Note 74, “Component and Measurement Advances
Ensure 16-Bit DAC Settling Time.”
Note 6: Measured at the major carry transition, 0V to 5V range. Output
amplifier: LT1469; CFB = 27pF.
Note 7. Full-scale transition; REF = 0V.
Note 8. REF = 6VRMS at 1kHz. 0V to 5V range. DAC code = FS. Output
amplifier = LT1469.
Note 9. Calculation from Vn = √4kTRB, where k = 1.38E-23 J/°K
(Boltzmann constant), R = resistance (
W), T = temperature (°K), and B =
bandwidth (Hz).
Note 10. Guaranteed by design. Not production tested.
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