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| 型號(hào)： | DAC1617D1G0HN |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | Dual 16-bit DAC: up to 1 Gsps; x2, x4 and x8 interpolating |
| 封裝： | DAC1617D1G0HN/C1<SOT813-3 (HVQFN72)|<<http://www.nxp.com/packages/SOT813-3.html<1<Always Pb-free,;DAC1617D1G0HN/C1<SOT813-3 (HVQFN72)|<<http://www.nxp.com/packages/SOT813 |
| 文件頁(yè)數(shù)： | 38/66頁(yè) |
| 文件大?。?/td> | 519K |
| 代理商： | DAC1617D1G0HN |
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10.18.2
Page 0 register allocation map
D
A
O
R
3
N
D
D
Table 21
shows an overview of all registers on page 0 (00h in hexadecimal).
Table 21.
Address
Page_00 register allocation map
Register name
R/W
Bit definition
Bit 4
-
Default
Bin
Bit 7
3W_SPI
Bit 6
SPI_RST
Bit 5
-
Bit 3
-
Bit 2
CODING
Bit 1
IC_PON
Bit 0
Hex
87h
0
00h
COMMON
R/W
GAP_PON 1000
0111
1
01h
TXCFG
R/W
NCO_ON
NCO_LP
_SEL
PLL_BUF
_PD
INV_SIN
_SEL
PLL_PLL
_PD
MODULATION[2:0]
INTERPOLATION[1:0] 0000
0001
1010
0001
0110
0110
0110
0110
0110
0110
0010
0110
0010
0110
0000
0000
0000
0000
1101
0100
0000
1011
1101
0100
0000
0010
0000
0000
01h
2
02h
PLLCFG
R/W
PLL_BP
PLL_DIV[1:0]
PLL_PHASE[1:0]
PLL_
OSC_PD
A1h
4
04h
FREQNCO_B0
R/W
FREQ_NCO[7:0]
66h
5
05h
FREQNCO_B1
R/W
FREQ_NCO[15:8]
66h
6
06h
FREQNCO_B2
R/W
FREQ_NCO[23:16]
66h
7
07h
FREQNCO_B3
R/W
FREQ_NCO[31:24]
66h
8
08h
FREQNCO_B4
R/W
FREQ_NCO[39:32]
26h
9
09h
PH_CORR_CTL0
R/W
PHASE_COR[7:0]
00h
10
0Ah
PH_CORR_CTL1
R/W
PH_COR
_ENA
-
-
PHASE_COR[12:8]
00h
11
0Bh
DAC_A_DGAIN_LSB
R/W
DAC_A_DGAIN[7:0]
50h
12
0Ch
DAC_A_DGAIN_MSB
R/W
-
-
-
-
DAC_A_DGAIN[11:8]
0Bh
13
0Dh
DAC_B_DGAIN_LSB
R/W
DAC_B_DGAIN[7:0]
50h
14
0Eh
DAC_B_DGAIN_MSB
R/W
-
-
-
-
DAC_B_DGAIN[11:8]
0Bh
15
0Fh
DAC_OUT_CTRL
R/W
-
-
-
-
A_DGAIN_E
B_DGAIN_E
MINUS
_3DB
CLIPPING
_ENA
00h
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