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| 型號： | DAC1405D650HW |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | Dual 14-bit DAC, up to 650 Msps; 2x 4x and 8x interpolating |
| 封裝： | DAC1405D650HW/C1<SOT638-1 (HTQFP100)|<<http://www.nxp.com/packages/SOT638-1.html<1<Always Pb-free,;DAC1405D650HW/C1<SOT638-1 (HTQFP100)|<<http://www.nxp.com/packages/SOT6 |
| 文件頁數(shù)： | 30/45頁 |
| 文件大?。?/td> | 1033K |
| 代理商： | DAC1405D650HW |
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DAC1405D650
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 3 — 10 September 2010
30 of 45
NXP Semiconductors
DAC1405D650
Dual 14-bit DAC, up to 650 Msps; 2
×
, 4
×
and 8
×
interpolating
The settings applied to DAC_A_GAIN_FINE[5:0] (register 0Ah; see
Table 20
“DAC_A_Cfg_2 register (address 0Ah) bit description”
) and to DAC_B_GAIN_FINE[5:0]
(register 0Dh; see
Table 23 “DAC_B_Cfg_2 register (address 0Dh) bit description”
) define
the fine variation of the full-scale current (see
Table 37 “I
O(fs)
fine adjustment”
).
Table 37.
Default settings are shown highlighted.
DAC_GAIN_FINE[5:0]
Decimal
32
The coding of the fine gain adjustment is two’s complement.
10.11 Digital offset adjustment
When the DAC1405D650 analog output is DC connected to the next stage, the digital
offset correction can be used to adjust the common mode level at the output of the DAC. It
adds an offset at the end of the digital part, just before the DAC.
The settings applied to DAC_A_OFFSET[11:0] (register 09h; see
Table 19
“DAC_A_Cfg_1 register (address 09h) bit description”
and register 0Bh; see
Table 21
“DAC_A_Cfg_3 register (address 0Bh) bit description”
) and to “DAC_B_OFFSET[11:0]”
(register 0Ch; see
Table 22 “DAC_B_Cfg_1 register (address 0Ch) bit description”
and
register 0Eh; see
Table 24 “DAC_B_Cfg_3 register (address 0Eh) bit description”
) define
the range of variation of the digital offset (see
Table 38 “Digital offset adjustment”
).
8
9
10
11
12
13
14
15
1000
1001
1010
1011
1100
1101
1110
1111
12.8
14.2
15.6
17.0
18.5
20.0
21.0
22.0
I
O(fs)
fine adjustment
Delta I
O(fs)
Two’s complement
10 0000
10 %
...
0
...
31
...
00 0000
...
01 1111
...
0
...
+10 %
Table 36.
Default settings are shown highlighted.
DAC_GAIN_COARSE[3:0]
Decimal
I
O(fs)
coarse adjustment
…continued
I
O(fs)
(mA)
Binary
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DAC1405D650HW/C1,5 | 功能描述:數(shù)模轉(zhuǎn)換器- DAC IC DAC 14BIT 650MSPD DL RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| DAC1405D650HW-C1 | 制造商:Integrated Device Technology Inc 功能描述:HTQFP100 - Bulk |
| DAC1405D650HW-C18 | 制造商:Integrated Device Technology Inc 功能描述:HTQFP100 - Tape and Reel |
| DAC1405D750 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Dual 14-bit DAC, up to 750 Msps; 4× and 8× interpolating |
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