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| 型號： | DAC1205D650HW |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | Dual 12-bit DAC, up to 650 Msps; 2x 4x and 8x interpolating |
| 封裝： | DAC1205D650HW/C1<SOT638-1 (HTQFP100)|<<http://www.nxp.com/packages/SOT638-1.html<1<Always Pb-free,;DAC1205D650HW/C1<SOT638-1 (HTQFP100)|<<http://www.nxp.com/packages/SOT6 |
| 文件頁數(shù)： | 24/43頁 |
| 文件大?。?/td> | 295K |
| 代理商： | DAC1205D650HW |
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DAC1205D650
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 13 September 2010
24 of 43
NXP Semiconductors
DAC1205D650
Dual 12-bit DAC, up to 650 Msps; 2
×
4
×
and 8
×
interpolating
10.5 Timing
The DAC1205D650 can operate at an update rate (f
s
) of up to 650 Msps and with an input
data rate (f
data
) of up to 160 MHz. The input timing is shown in
Figure 10 “Input timing
diagram”
.
The typical performances are measured at 50 % duty cycle but any timing within the limits
of the characteristics will not alter the performance.
In
Table 31 “Frequencies”
, the links between internal and external clocking are defined.
The setting applied to PLL_DIV[1:0] (register 02h[4:3]; see
Table 12 “PLLCFG register
(address 02h) bit description”
) allows the frequency between the digital part and the DAC
core to be adjusted.
Table 31.
Mode
The settings applied to PLL_PHASE[1:0] (register 02h[2:1]) and PLL_POL
(register 02h[0]), allows adjustment of the phase and polarity of the sampling clock. This
occurs at the input of the DAC core and depends mainly on the sampling frequency. Some
examples are given in
Table 32 “Sample clock phase and polarity examples”
.
Table 32.
Mode
n in Qn = 0 to 11 and for In = 0 to 11.
Fig 10. Input timing diagram
Frequencies
CLK input
(MHz)
160
160
80
320
320
160
Input data rate
(MHz)
160
160
80
320
320
160
Interpolation
Update rate
(Msps)
320
640
640
320
640
640
PLL_DIV[1:0]
Dual-port
Dual-port
Dual-port
Interleaved
Interleaved
Interleaved
2
×
4
×
8
×
2
×
4
×
8
×
01 (/4)
01 (/4)
10 (/8)
00 (/2)
00 (/2)
01 (/4)
Sample clock phase and polarity examples
Input data rate
(MHz)
80
80
80
160
160
160
Interpolation
Update rate
(Msps)
160
320
640
160
320
640
PLL_PHASE
[1:0]
01
01
01
01
01
01
PLL_POL
Dual-port
Dual-port
Dual-port
Interleaved
Interleaved
Interleaved
2
×
4
×
8
×
2
×
4
×
8
×
1
0
1
1
0
1
001aaj815
N
t
su(i)
90 %
50 %
90 %
In/Qn
CLK
(CLKP-CLKN)
t
h(i)
t
w(CLK)
N + 1
N + 2
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DAC1205D650HW/C1 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Dual 12-bit DAC, up to 650 Msps; 2′ 4′ and 8′ interpolating |
| DAC1205D650HW/C1,5 | 功能描述:數(shù)模轉(zhuǎn)換器- DAC IC DAC 12BIT 650MSPS DL RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| DAC1205D650HW-C1 | 功能描述:數(shù)模轉(zhuǎn)換器- DAC DAC RoHS:否 制造商:IDT 轉(zhuǎn)換器數(shù)量:2 DAC 輸出端數(shù)量:4 轉(zhuǎn)換速率:650 MSPs 分辨率:12 bit 接口類型:Serial, SPI 穩(wěn)定時間:20 ns 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-100 封裝: |
| DAC1205D650HW-C18 | 制造商:Integrated Device Technology Inc 功能描述:BST - Tape and Reel |
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