參數(shù)資料
型號: DAC1005D750HW
廠商: NXP Semiconductors N.V.
元件分類: 外設(shè)及接口
英文描述: Dual 10-bit DAC, up to 750 Msps; 2x 4x and 8x interpolating
封裝: DAC1005D750HW/C1<SOT638-1 (HTQFP100)|<<http://www.nxp.com/packages/SOT638-1.html<1<Always Pb-free,;DAC1005D750HW/C1<SOT638-1 (HTQFP100)|<<http://www.nxp.com/packages/SOT6
文件頁數(shù): 31/42頁
文件大?。?/td> 353K
代理商: DAC1005D750HW
DAC1005D750
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 7 June 2011
31 of 42
NXP Semiconductors
DAC1005D750
Dual 10-bit DAC, up to 750 Msps; 4x and 8x interpolating
Table 41.
Default settings are shown highlighted.
DAC_OFFSET[8:0]
Decimal
256
255
...
1
0
+1
...
+254
+255
10.12 Analog output
The DAC1005D750 has two output channels each of which produces two complementary
current outputs. These allow the even-order harmonics and noise to be reduced. The pins
are IOUTAP/IOUTAN and IOUTBP/IOUTBN, respectively and need to be connected via a
load resistor R
L
to the 3.3 V analog power supply (V
DDA(3V3)
).
Refer to
Figure 12
for the equivalent analog output circuit of one DAC. This circuit consists
of a parallel combination of NMOS current sources, and their associated switches, for
each segment.
The cascode source configuration increases the output impedance of the source, thus
improving the dynamic performance of the DAC by introducing less distortion.
The device can provide an output level of up to 2 V
o(p-p)
depending on the application, the
following stages and the targeted performances.
Digital offset adjustment
Offset applied
Two’s complement
1 0000 0000
1 0000 0001
...
1 1111 1111
0 0000 0000
0 0000 0001
...
0 1111 1110
0 1111 1111
256
255
...
1
0
+1
...
+254
+255
Fig 12. Equivalent analog output circuit (one DAC)
001aah019
V
DDA(3V3)
AGND
IOUTAP/IOUTBP
IOUTAN/IOUTBN
RL
RL
AGND
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