參數(shù)資料
型號: DAC1005D750HW
廠商: NXP Semiconductors N.V.
元件分類: 外設(shè)及接口
英文描述: Dual 10-bit DAC, up to 750 Msps; 2x 4x and 8x interpolating
封裝: DAC1005D750HW/C1<SOT638-1 (HTQFP100)|<<http://www.nxp.com/packages/SOT638-1.html<1<Always Pb-free,;DAC1005D750HW/C1<SOT638-1 (HTQFP100)|<<http://www.nxp.com/packages/SOT6
文件頁數(shù): 23/42頁
文件大?。?/td> 353K
代理商: DAC1005D750HW
DAC1005D750
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 7 June 2011
23 of 42
NXP Semiconductors
DAC1005D750
Dual 10-bit DAC, up to 750 Msps; 4x and 8x interpolating
In Interleaved mode, both DACs use the same data input at twice the Dual-port mode
frequency. Data enters the latch on the rising edge of the internal clock signal. The data is
sent to either latch I or latch Q, depending on the SELIQ signal.
The SELIQ input (pin 41) allows the synchronization of the internally demultiplexed I and
Q channels; see
Figure 7 “Interleaved mode timing (8x interpolation, latch on rising
edge)”
.
The SELIQ signal can be either synchronous or asynchronous (single rising edge, single
pulse). The first data following the SELIQ rising edge is sent in channel I and following
data is sent in channel Q. After this, data is distributed alternately between these
channels.
Fig 6.
Interleaved mode operation
CLK
dig
= internal digital clock
Interleaved mode timing (8x interpolation, latch on rising edge)
Fig 7.
001aam219
LATCH
I
2
×
2
×
2
×
FIR 1
FIR 1
FIR 2
FIR 2
FIR 3
FIR 3
LATCH
Q
2
×
2
×
2
×
I9 to I0
Q9/SELIQ
001aaj814
N
In
SELIQ
(synchronous alternative)
SELIQ
(asynchronous alternative 1)
SELIQ
(asynchronous alternative 2)
CLK
dig
Latch I output
Latch Q output
XX
N
N + 2
N + 1
N + 2
N + 3
N + 4
N + 5
XX
N + 1
N + 3
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