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參數(shù)資料
| 型號： | CY7C1371BV25-83BGC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 512K X 36 ZBT SRAM, 10 ns, PBGA119 |
| 封裝： | 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119 |
| 文件頁數(shù)： | 23/25頁 |
| 文件大?。?/td> | 709K |
| 代理商： | CY7C1371BV25-83BGC |
CY7C1373BV25
CY7C1371BV25
Document #: 38-05250 Rev. *A
Page 7 of 25
On the next clock rise the data presented to DQ and DP (or a
subset for byte write operations, see Write Cycle Description
table for details) inputs is latched into the device and the write
is complete. Additional accesses (Read/Write/Deselect) can
be initiated on this cycle.
The data written during the Write operation is controlled by
Byte
Write
Select
signals.
The
CY7C1371BV25/
CY7C1373BV25 provide byte write capability that is described
in the Write Cycle Description table. Asserting the Write
Enable input (WE) with the selected Byte Write Select input
will selectively write to only the desired bytes. Bytes not
selected during a byte write operation will remain unaltered. A
synchronous self-timed write mechanism has been provided
to simplify the write operations. Byte write capability has been
included in order to greatly simplify Read/Modify/Write
sequences, which can be reduced to simple byte write opera-
tions.
Because the CY7C1371BV25/CY7C1373BV25 are common
I/O devices, data should not be driven into the device while the
outputs are active. The Output Enable (OE) can be deasserted
HIGH before presenting data to the DQ and DP inputs. Doing
so will three-state the output drivers. As a safety precaution,
DQ and DP are automatically three-stated during the data
portion of a write cycle, regardless of the state of OE.
Burst Write Accesses
The CY7C1371BV25/CY7C1373BV25 has an on-chip burst
counter that allows the user the ability to supply a single
address and conduct up to four Write operations without
reasserting the address inputs. ADV/LD must be driven LOW
in order to load the initial address, as described in the Single
Write Access section above. When ADV/LD is driven HIGH on
the subsequent clock rise, the chip enables (CE1, CE2, and
CE3) and WE inputs are ignored and the burst counter is incre-
mented. The correct BWSa,b,c,d/BWSa,b inputs must be driven
in each cycle of the burst write in order to write the correct
bytes of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CEs, ADSP, and ADSC must remain
inactive for the duration of tZZREC after the ZZ input returns
LOW.
Cycle Description Truth Table[1, 2, 3, 4, 5, 6]
Operation
Address
used
CE
CEN
ADV/
LD
WE
BWSx
CLK
Comments
Deselected
External
1
0
X
L-H
I/Os three-state following next recog-
nized clock.
Suspend
–
X
1
X
L-H
Clock ignored, all operations
suspended.
Begin Read
External
0
1
X
L-H
Address latched.
Begin Write
External
0
Valid
L-H
Address latched, data presented two
valid clocks later.
Burst READ
Operation
Internal
X
0
1
X
L-H
Burst Read operation. Previous
access was a Read operation.
Addresses incremented internally in
conjunction with the state of MODE.
Burst WRITE
Operation
Internal
X
0
1
X
Valid
L-H
Burst Write operation. Previous
access was a Write operation.
Addresses incremented internally in
conjunction with the state of MODE.
Bytes written are determined by
BWSa,b,c,d/BWSa,b.
Interleaved Burst Sequence
First
Address
Second
Address
Third
Address
Fourth
Address
A[1:0]
00
01
10
11
01
00
11
10
11
00
01
11
10
01
00
Linear Burst Sequence
First
Address
Second
Address
Third
Address
Fourth
Address
A[1:0]
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1371C-100AC | 功能描述:IC SRAM 18MBIT 100MHZ 100LQFP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:96 系列:- 格式 - 存儲器:閃存 存儲器類型:FLASH 存儲容量:16M（2M x 8，1M x 16） 速度:70ns 接口:并聯(lián) 電源電壓:2.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應(yīng)商設(shè)備封裝:48-TSOP 包裝:托盤 |
| CY7C1371C-100AIT | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Quad 3.3V 18M-Bit 512K x 36 8.5ns 100-Pin TQFP T/R |
| CY7C1371C-100BZC | 制造商:Rochester Electronics LLC 功能描述:16MB (512KX36) 3.3V NOBL-FT SRAM - Bulk 制造商:Cypress Semiconductor 功能描述: |
| CY7C1371C-117BGC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Quad 3.3V 18M-Bit 512K x 36 7.5ns 119-Pin BGA 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Single 3.3V 18M-Bit 512K x 36 7.5ns 119-Pin BGA 制造商:Rochester Electronics LLC 功能描述:16MB (512KX36) 3.3V NOBL-FT SRAM - Bulk |
| CY7C1371C-133BGC | 制造商:Rochester Electronics LLC 功能描述:16MB (512KX36) 3.3V NOBL-FT SRAM - Bulk 制造商:Cypress Semiconductor 功能描述: |
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