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參數(shù)資料
| 型號(hào)： | CY7C1371BV25-83BGC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 512K X 36 ZBT SRAM, 10 ns, PBGA119 |
| 封裝： | 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119 |
| 文件頁數(shù)： | 22/25頁 |
| 文件大?。?/td> | 709K |
| 代理商： | CY7C1371BV25-83BGC |
CY7C1373BV25
CY7C1371BV25
Document #: 38-05250 Rev. *A
Page 6 of 25
Functional Overview
The CY7C1371BV25/CY7C1373BV25 is a Synchronous
Flow-Through Burst NoBL SRAM designed specifically to
eliminate wait states during Write-Read transitions. All
synchronous inputs pass through input registers controlled by
the rising edge of the clock. The clock signal is qualified with
the Clock Enable input signal (CEN). If CEN is HIGH, the clock
signal is not recognized and all internal states are maintained.
All synchronous operations are qualified with CEN. Maximum
access delay from the clock rise (tCDV) is 6.5 ns (133-MHz
device).
Accesses can be initiated by asserting Chip Enable(s) (CE1,
CE2, CE3 on the TQFP, CE1 on the BGA) active at the rising
edge of the clock. If Clock Enable (CEN) is active LOW and
ADV/LD is asserted LOW, the address presented to the device
will be latched. The access can either be a Read or Write
operation, depending on the status of the Write Enable (WE).
Byte Write Selects can be used to conduct byte write opera-
tions.
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self-timed write
circuitry
Synchronous Chip Enable (CE1, CE2, and CE3 on the TQFP,
CE1 on the BGA) and an asynchronous Output Enable (OE)
simplify depth expansion. All operations (Reads, Writes, and
Deselects) are pipelined. ADV/LD should be driven LOW once
the device has been deselected in order to load a new address
for the next operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2,
and CE3 are ALL asserted active, (3) the Write Enable input
signal WE is deasserted HIGH, and 4) ADV/LD is asserted
LOW. The address presented to the address inputs is latched
into the Address Register and presented to the memory core
and control logic. The control logic determines that a read
access is in progress and allows the requested data to
propagate to the output buffers. The data is available within
6.5 ns (133-MHz device) provided OE is active LOW. After the
first clock of the read access the output buffers are controlled
by OE and the internal control logic. OE must be driven LOW
in order for the device to drive out the requested data. On the
subsequent clock, another operation (Read/Write/Deselect)
can be initiated. When the SRAM is deselected at clock rise
by one of the chip enable signals, its output will be three-stated
immediately.
Burst Read Accesses
The CY7C1371BV25/CY7C1373BV25 has an on-chip burst
counter that allows the user the ability to supply a single
address and conduct up to four Reads without reasserting the
address inputs. ADV/LD must be driven LOW in order to load
a new address into the SRAM, as described in the Single Read
Access section above. The sequence of the burst counter is
determined by the MODE input signal. A LOW input on MODE
selects a linear burst mode, a HIGH selects an interleaved
burst sequence. Both burst counters use A0 and A1 in the
burst sequence, and will wrap-around when incremented suffi-
ciently. A HIGH input on ADV/LD will increment the internal
burst counter regardless of the state of chip enables inputs or
WE. WE is latched at the beginning of a burst cycle. Therefore,
the type of access (Read or Write) is maintained throughout
the burst sequence.
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) Chip
Enable(s) asserted active, and (3) the write signal WE is
asserted LOW. The address presented is loaded into the
Address Register. The write signals are latched into the
Control Logic block. The data lines are automatically
three-stated regardless of the state of the OE input signal. This
allows the external logic to present the data on DQ and DP.
VDDQ
I/O Power
Supply
Power supply for the I/O circuitry.
VSS
Ground
Ground for the device. Should be connected to ground of the system.
TDO
JTAG serial output
Synchronous
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK (BGA
only).
TDI
JTAG serial input
Synchronous
Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK (BGA only).
TMS
Test Mode Select
Synchronous
This pin controls the Test Access Port state machine. Sampled on the rising edge of
TCK (BGA only).
TCK
JTAG serial
clock
Serial clock to the JTAG circuit (BGA only)
32M
64M
128M
–
No connects. Reserved for address expansion.
NC
–
No connects. Pins are not internally connected.
DNU
–
Do not use pins.
Pin Definitions (100-Pin TQFP) (continued)
Pin Name
I/O Type
Pin Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C341B-25JC | OT PLD, 40 ns, PQCC84 |
| CY7C341B-25JI | OT PLD, 40 ns, PQCC84 |
| CY7C341B-35JC | OT PLD, 55 ns, PQCC84 |
| CY7C341B-35JI | OT PLD, 55 ns, PQCC84 |
| CY7C341B-25RC | UV PLD, 40 ns, CPGA84 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1371C-100AC | 功能描述:IC SRAM 18MBIT 100MHZ 100LQFP RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:96 系列:- 格式 - 存儲(chǔ)器:閃存 存儲(chǔ)器類型:FLASH 存儲(chǔ)容量:16M（2M x 8，1M x 16） 速度:70ns 接口:并聯(lián) 電源電壓:2.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應(yīng)商設(shè)備封裝:48-TSOP 包裝:托盤 |
| CY7C1371C-100AIT | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Quad 3.3V 18M-Bit 512K x 36 8.5ns 100-Pin TQFP T/R |
| CY7C1371C-100BZC | 制造商:Rochester Electronics LLC 功能描述:16MB (512KX36) 3.3V NOBL-FT SRAM - Bulk 制造商:Cypress Semiconductor 功能描述: |
| CY7C1371C-117BGC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Quad 3.3V 18M-Bit 512K x 36 7.5ns 119-Pin BGA 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Single 3.3V 18M-Bit 512K x 36 7.5ns 119-Pin BGA 制造商:Rochester Electronics LLC 功能描述:16MB (512KX36) 3.3V NOBL-FT SRAM - Bulk |
| CY7C1371C-133BGC | 制造商:Rochester Electronics LLC 功能描述:16MB (512KX36) 3.3V NOBL-FT SRAM - Bulk 制造商:Cypress Semiconductor 功能描述: |
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