- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄223638 > CY7C1371BV25-83BGC (CYPRESS SEMICONDUCTOR CORP) 512K X 36 ZBT SRAM, 10 ns, PBGA119 PDF資料下載
參數(shù)資料
| 型號： | CY7C1371BV25-83BGC |
| 廠商： | CYPRESS SEMICONDUCTOR CORP |
| 元件分類： | SRAM |
| 英文描述： | 512K X 36 ZBT SRAM, 10 ns, PBGA119 |
| 封裝： | 14 X 22 MM, 2.40 MM HEIGHT, PLASTIC, BGA-119 |
| 文件頁數(shù)： | 21/25頁 |
| 文件大小： | 709K |
| 代理商： | CY7C1371BV25-83BGC |
CY7C1373BV25
CY7C1371BV25
Document #: 38-05250 Rev. *A
Page 5 of 25
Pin Definitions (100-Pin TQFP)
Pin Name
I/O Type
Pin Description
A0
A1
A
Input-
Synchronous
Address Inputs used to select one of the 266,144 address locations. Sampled at the
rising edge of the CLK.
BWSa
BWSb
BWSc
BWSd
Input-
Synchronous
Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the
SRAM. Sampled on the rising edge of CLK. BWSa controls DQa and DPa, BWSb
controls DQb and DPb, BWSc controls DQc and DPc, BWSd controls DQd and DPd.
WE
Input-
Synchronous
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active
LOW. This signal must be asserted LOW to initiate a write sequence.
ADV/LD
Input-
Synchronous
Advance/Load input used to advance the on-chip address counter or load a new
address. When HIGH (and CEN is asserted LOW) the internal burst counter is
advanced. When LOW, a new address can be loaded into the device for an access.
After being deselected, ADV/LD should be driven LOW in order to load a new address.
CLK
Input-Clock
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified
with CEN. CLK is only recognized if CEN is active LOW.
CE1
Input-
Synchronous
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE2 and CE3 to select/deselect the device.
CE2
Input-
Synchronous
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE3 to select/deselect the device.
CE3
Input-
Synchronous
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE2 to select/deselect the device.
OE
Input-
Asynchronous
Output Enable, active LOW. Combined with the synchronous logic block inside the
device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to
behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input
data pins. OE is masked during the data portion of a write sequence, during the first
clock when emerging from a deselected state and when the device has been
deselected.
CEN
Input-
Synchronous
Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized
by the SRAM. When deasserted HIGH the clock signal is masked. Since deasserting
CEN does not deselect the device, CEN can be used to extend the previous cycle when
required.
DQa
DQb
DQc
DQd
I/O-
Synchronous
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by A[x] during the previous clock rise of the read cycle. The
direction of the pins is controlled by OE and the internal control logic. When OE is
asserted LOW, the pins can behave as outputs. When HIGH, DQa–DQd are placed in
a three-state condition. The outputs are automatically three-stated during the data
portion of a write sequence, during the first clock when emerging from a deselected
state, and when the device is deselected, regardless of the state of OE. DQ a,b,c and
d are 8 bits wide.
DPa
DPb
DPc
DPd
I/O-
Synchronous
Bidirectional Data Parity I/O lines. Functionally, these signals are identical to
DQ[31:0]. During write sequences, DPa is controlled by BWSa, DPb is controlled by
BWSb, DPc is controlled by BWSc, and DPd is controlled by BWSd. DP a,b,c and d
are 1 bit wide
ZZ
Input-
Asynchronous
ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep”
condition with data integrity preserved.
MODE
Input-pin
Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved
burst order. Pulled LOW selects the linear burst order. MODE should not change states
during operation. When left floating MODE will default HIGH, to an interleaved burst
order.
VDD
Power Supply
Power supply inputs to the core of the device.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CY7C341B-25JC | OT PLD, 40 ns, PQCC84 |
| CY7C341B-25JI | OT PLD, 40 ns, PQCC84 |
| CY7C341B-35JC | OT PLD, 55 ns, PQCC84 |
| CY7C341B-35JI | OT PLD, 55 ns, PQCC84 |
| CY7C341B-25RC | UV PLD, 40 ns, CPGA84 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY7C1371C-100AC | 功能描述:IC SRAM 18MBIT 100MHZ 100LQFP RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:96 系列:- 格式 - 存儲(chǔ)器:閃存 存儲(chǔ)器類型:FLASH 存儲(chǔ)容量:16M（2M x 8，1M x 16） 速度:70ns 接口:并聯(lián) 電源電壓:2.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-TFSOP（0.724"，18.40mm 寬） 供應(yīng)商設(shè)備封裝:48-TSOP 包裝:托盤 |
| CY7C1371C-100AIT | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Quad 3.3V 18M-Bit 512K x 36 8.5ns 100-Pin TQFP T/R |
| CY7C1371C-100BZC | 制造商:Rochester Electronics LLC 功能描述:16MB (512KX36) 3.3V NOBL-FT SRAM - Bulk 制造商:Cypress Semiconductor 功能描述: |
| CY7C1371C-117BGC | 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Quad 3.3V 18M-Bit 512K x 36 7.5ns 119-Pin BGA 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Single 3.3V 18M-Bit 512K x 36 7.5ns 119-Pin BGA 制造商:Rochester Electronics LLC 功能描述:16MB (512KX36) 3.3V NOBL-FT SRAM - Bulk |
| CY7C1371C-133BGC | 制造商:Rochester Electronics LLC 功能描述:16MB (512KX36) 3.3V NOBL-FT SRAM - Bulk 制造商:Cypress Semiconductor 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。