參數(shù)資料
型號(hào)： CY7C0832V-167AXC
廠(chǎng)商： CYPRESS SEMICONDUCTOR CORP
元件分類(lèi)： SRAM
英文描述： 256K X 18 DUAL-PORT SRAM, 4 ns, PQFP120
封裝： 14 X 14 MM, 1.40 MM HEIGHT, LEAD FREE, TQFP-120
文件頁(yè)數(shù)： 14/32頁(yè)
文件大?。?/td> 895K
代理商： CY7C0832V-167AXC
CY7C0851V/CY7C0852V
CY7C0831V/CY7C0832V
Document #: 38-06059 Rev. *I
Page 21 of 32
Bank Select Read[25, 26]
Read-to-Write-to-Read (OE = LOW)[24, 27, 28, 29, 30]
Notes:
25. In this depth-expansion example, B1 represents Bank #1 and B2 is Bank #2; each bank consists of one Cypress CY7C0851V/CY7C0852V device from this data
sheet. ADDRESS(B1) = ADDRESS(B2).
26.
ADS = CNTEN= B0 – B3 = OE = LOW; MRST = CNTRST = CNT/MSK = HIGH.
27. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals.
28. During “No Operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.
29.
CE0 = OE = B0 – B3 = LOW; CE1 = R/W = CNTRST = MRST = HIGH.
30. CE0 = B0 – B3 = R/W = LOW; CE1 = CNTRST = MRST = CNT/MSK = HIGH. When R/W first switches low, since OE = LOW, the Write operation cannot be
completed (labelled as no operation). One clock cycle is required to three-state the I/O for the Write operation on the next rising edge of CLK.
Switching Waveforms (continued)
Q3
Q1
Q0
Q2
A0
A1
A2
A3
A4
A5
Q4
A0
A1
A2
A3
A4
A5
tSA
tHA
tSC
tHC
tSA
tHA
tSC
tHC
tSC
tHC
tSC tHC
tCKHZ
tDC
tCD2
tCKLZ
tCD2
tCKHZ
tCKLZ
tCD2
tCKHZ
tCKLZ
tCD2
tCH2
tCL2
tCYC2
CLK
ADDRESS(B1)
CE(B1)
DATAOUT(B2)
DATAOUT(B1)
ADDRESS(B2)
CE(B2)
tCYC2
tCL2
tCH2
tHC
tSC
tHW
tSW
tHA
tSA
tHW
tSW
tCD2
tCKHZ
tSD tHD
tCKLZ
tCD2
NO OPERATION
WRITE
READ
CLK
CE
R/W
ADDRESS
DATAIN
DATAOUT
An
An+1
An+2
Dn+2
An+3
An+4
Qn
Qn+3
相關(guān)PDF資料
PDF描述
CY7C0851AV-133AXC FLEx36™ 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
CY7C0851AV-133BBC FLEx36™ 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
CY7C0851AV-167AXC FLEx36™ 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
CY7C0851AV-167BBC FLEx36™ 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
CY7C0852AV-133BBC FLEx36™ 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CY7C0832V-167BBC 制造商:Cypress Semiconductor 功能描述:SRAM SYNC DUAL 3.3V 4.5MBIT 256KX18 4NS 144FBGA - Bulk
CY7C0833AV-100BBC 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Dual 3.3V 9M-Bit 512K x 18 144-Pin FBGA
CY7C0833AV-133BBC 制造商:Cypress Semiconductor 功能描述:SRAM Chip Sync Dual 3.3V 9M-Bit 512K x 18 4.7ns 144-Pin FBGA 制造商:Rochester Electronics LLC 功能描述:
CY7C0833AV-133BBI 制造商:Cypress Semiconductor 功能描述:
CY7C0833V-100BBC 制造商:Cypress Semiconductor 功能描述:SRAM SYNC DUAL 3.3V 9MBIT 512KX18 5NS 144FBGA - Bulk
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠(chǎng)商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*