參數(shù)資料
型號(hào): CY7C0832V-167AXC
廠商: CYPRESS SEMICONDUCTOR CORP
元件分類: SRAM
英文描述: 256K X 18 DUAL-PORT SRAM, 4 ns, PQFP120
封裝: 14 X 14 MM, 1.40 MM HEIGHT, LEAD FREE, TQFP-120
文件頁數(shù): 13/32頁
文件大?。?/td> 895K
代理商: CY7C0832V-167AXC
CY7C0851V/CY7C0852V
CY7C0831V/CY7C0832V
Document #: 38-06059 Rev. *I
Page 20 of 32
Read Cycle[6, 21, 22, 23, 24]
Notes:
21. OE is asynchronously controlled; all other inputs (excluding MRST and JTAG) are synchronous to the rising clock edge.
22. ADS = CNTEN = LOW, and MRST = CNTRST = CNT/MSK = HIGH.
23. The output is disabled (high-impedance state) by CE = VIH following the next rising edge of the clock.
24. Addresses do not have to be accessed sequentially since ADS = CNTEN = VIL with CNT/MSK = VIH constantly loads the address on the rising edge of the CLK.
Numbers are for reference only.
Switching Waveforms (continued)
tCH2
tCL2
tCYC2
tSC
tHC
tSW
tHW
tSA
tHA
An
An+1
CLK
CE
R/W
ADDRESS
DATAOUT
OE
An+2
An+3
tSC
tHC
tOHZ
tOE
tOLZ
tDC
tCD2
tCKLZ
Qn
Qn+1
Qn+2
1 Latency
B0–B3
tSB
tHB
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