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參數(shù)資料
| 型號： | CY28446LFXC |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 2/19頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK CALISTOGA CK410M 64QFN |
| 標(biāo)準(zhǔn)包裝： | 260 |
| 類型： | 時鐘/頻率發(fā)生器 |
| PLL： | 是 |
| 主要目的： | Intel CPU 服務(wù)器 |
| 輸入： | LVTTL，晶體 |
| 輸出： | HCSL，LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 3:20 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 200MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 64-QFN（9x9） |
| 包裝： | 托盤 |
CY28446
.....................Document #: 001-00168 Rev *F Page 10 of 19
PD (Power down) Clarification
The CKPWRGD/PWRDWN# pin is a dual-function pin. During
initial power-up, the pin functions as CKPWRGD. Once
CKPWRGD has been sampled HIGH by the clock chip, the pin
assumes PD# functionality. The PD# pin is an asynchronous
active LOW input used to shut off all clocks cleanly before
shutting off power to the device. This signal is synchronized
internal to the device before powering down the clock synthe-
sizer. PD# is also an asynchronous input for powering up the
system. When PD# is asserted LOW, all clocks need to be
driven to a LOW value and held before turning off the VCOs
and the crystal oscillator.
PD (Power down) Assertion
When PD is sampled HIGH by two consecutive rising edges
of CPUC, all single-ended outputs will be held LOW on their
next HIGH-to-LOW transition and differential clocks must held
HIGH or tri-stated (depending on the state of the control
register drive mode bit) on the next diff clock# HIGH-to-LOW
transition within 4 clock periods. When the SMBus PD drive
mode bit corresponding to the differential (CPU, SRC, and
DOT) clock output of interest is programmed to ‘0’, the clock
output are held with “Diff clock” pin driven HIGH and “Diff
clock#” driven LOW. If the control register PD drive mode bit
corresponding to the output of interest is programmed to “1”,
then both the “Diff clock” and the “Diff clock#” are LOW.
Figure 4 shows CPUT = 133 MHz and PD drive mode = ‘1’ for
all differential outputs. This diagram and description is appli-
cable to valid CPU frequencies 100, 133, 166 and 200 MHz. If
PD mode has the initial power-on state, PD must be asserted
HIGH in less than 10
s after asserting Vtt_PwrGd#. The
96_100_SSC follows the DOT waveform selected for 96 MHz
and the SRC waveform in 100 MHz mode.
The power-up latency is less than 1.8 ms. This is the time from
the deassertion of the PD pin or the ramping of the power
supply until the time that stable clocks are output from the
clock chip. All differential outputs stopped in a three-state
condition resulting from power-down will be driven HIGH in
less than 300
s of PD deassertion to a voltage greater than
200 mV. After the clock chip’s internal PLL is powered up and
locked, all outputs will be enabled within a few clock cycles of
each other. Figure 5 is an example showing the relationship of
clocks coming up. It should be noted that 96_100_SSC will
follow the DOT waveform is selected for 96 MHz and the SRC
waveform when in 100-MHz mode.
Figure 4. Power down Assertion Timing Waveform
PD
US B , 4 8 M H z
DO T9 6 T
D O T 96C
S RCT 1 0 0 M Hz
S R CC 1 0 0 M Hz
C P UT, 1 3 3 M Hz
P C I, 3 3 M H z
RE F
CP U C , 1 3 3 M Hz
Figure 5. Power-down Deassertion Timing Waveform
DO T 96C
PD
CP UC, 133M H z
CP UT , 133M H z
S RCC 100M H z
USB, 48M Hz
DO T 96T
S RCT 100M H z
Tstab le
<1 .8 ms
P C I, 33M H z
RE F
Tdrive_PW R D N #
<3 00
, >200 mV
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