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參數(shù)資料
| 型號： | CY28446LFXC |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 18/19頁 |
| 文件大小： | 0K |
| 描述： | IC CLOCK CALISTOGA CK410M 64QFN |
| 標(biāo)準(zhǔn)包裝： | 260 |
| 類型： | 時鐘/頻率發(fā)生器 |
| PLL： | 是 |
| 主要目的： | Intel CPU 服務(wù)器 |
| 輸入： | LVTTL，晶體 |
| 輸出： | HCSL，LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 3:20 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 200MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 64-QFN（9x9） |
| 包裝： | 托盤 |
CY28446
.......................Document #: 001-00168 Rev *F Page 8 of 19
.
The CY28446 requires a Parallel Resonance Crystal. Substi-
tuting a series resonance crystal causes the CY28446 to
operate at the wrong frequency and violate the ppm specifi-
cation. For most applications there is a 300-ppm frequency
shift between series and parallel crystals due to incorrect
loading
Crystal Loading
Crystal loading plays a critical role in achieving low ppm perfor-
mance. To realize low ppm performance, use the total capac-
itance the crystal sees to calculate the appropriate capacitive
loading (CL).
Figure 1 shows a typical crystal configuration using the two
trim capacitors. It is important that the trim capacitors are in
series with the crystal. It is not true that load capacitors are in
parallel with the crystal and are approximately equal to the
load capacitance of the crystal.
.
Calculating Load Capacitors
In addition to the standard external trim capacitors, consider
the trace capacitance and pin capacitance to calculate the
crystal loading correctly. Again, the capacitance on each side
Byte 8: Control Register 7
Bit
@Pup
Name
Description
7
0
Reserved
Reserved set to 0
6
1
SRC[T/C]10
SRC[T/C]10 Output Enable
0 = Disable (Tri-state), 1 = Enable
5
1
SRC[T/C]9
SRC[T/C]9 Output Enable
0 = Disable (Tri-state), 1 = Enable
4
1
SRC[T/C]8
SRC[T/C]8 Output Enable
0 = Disable (Tri-state), 1 = Enable
3
0
Reserved
Reserved set to 0
2
0
SRC10
Allow control of SRC[T/C]10 with assertion of OEA#
0 = Free running, 1 = Stopped with OEA#
1
0
SRC9
Allow control of SRC[T/C]9 with assertion of OEB#
0 = Free running, 1 = Stopped with OEB#
0
SRC8
Allow control of SRC[T/C]8 with assertion of OEA#
0 = Free running, 1 = Stopped with OEA#
Byte 9: Control Register 8
Bit
@Pup
Name
Description
7
0
PCI3
33-MHz Output drive strength
0 = Low, 1 = High
6
0
PCI2
33-MHz Output drive strength
0 = Low, 1 = High
5
0
PCI1
33-MHz Output drive strength
0 = Low, 1 = High
4
0
PCI0
33-MHz Output drive strength
0 = Low, 1 = High
3
0
PCIF0
33-MHz Output drive strength
0 = Low, 1 = High
2
1
Reserved
Reserved set to 1
1
Reserved
Reserved set to 1
0
1
Reserved
Reserved set to 1
Crystal Recommendations
Frequency
(Fund)
Cut
Loading
Load Cap
Drive
(max.)
Shunt Cap
(max.)
Motional
(max.)
Tolerance
(max.)
Stability
(max.)
Aging
(max.)
14.31818 MHz
AT
Parallel
20 pF
0.1 mW
5 pF
0.016 pF
35 ppm
30 ppm
5 ppm
Figure 1. Crystal Capacitive Clarification
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CY28446LFXCT | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Calistoga RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| CY28447 | 制造商:SPECTRALINEAR 制造商全稱:SPECTRALINEAR 功能描述:Clock Generator for Intel㈢ Calistoga Chipset |
| CY28447LFXC | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Calistoga System Clk Extra SRC Output RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| CY28447LFXCT | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Calistoga System Clk Extra SRC Output RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| CY28506OC | 制造商:Rochester Electronics LLC 功能描述:FTG FOR MOTHERBOARDS - Bulk |
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