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參數(shù)資料
| 型號： | CY28446LFXC |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 16/19頁 |
| 文件大小： | 0K |
| 描述： | IC CLOCK CALISTOGA CK410M 64QFN |
| 標準包裝： | 260 |
| 類型： | 時鐘/頻率發(fā)生器 |
| PLL： | 是 |
| 主要目的： | Intel CPU 服務器 |
| 輸入： | LVTTL，晶體 |
| 輸出： | HCSL，LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 3:20 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 200MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤 |
| 供應商設備封裝： | 64-QFN（9x9） |
| 包裝： | 托盤 |
CY28446
.......................Document #: 001-00168 Rev *F Page 6 of 19
0
CPU PLL Spread Enable PLL1 (CPU PLL) Spread Spectrum Enable
0 = Spread off
1 = Spread on (–0.5% spread spectrum on CPU/SRC/PCI clocks)
Byte 2: Control Register 2
Bit
@Pup
Name
Description
7
1
Reserved
Reserved set to 1
6
1
Reserved
Reserved set to 1
5
1
PCI3
PCI3 Output Enable
0 = Disable, 1 = Enable
4
1
PCI2
PCI2 Output Enable
0 = Disable, 1 = Enable
3
1
PCI1
PCI1Output Enable
0 = Disable, 1 = Enable
2
1
PCI0
PCI0 Output Enable
0 = Disable, 1 = Enable
1
Reserved
Reserved set to 1
0
1
Reserved
Reserved set to 1
Byte 3: Control Register 3
Bit
@Pup
Name
Description
7
0
SRC7
Allow control of SRC[T/C]7 with assertion of OEB#
0 = Free running, 1 = Stopped with OEB#
6
0
Reserved
Reserved set to 0
5
0
SRC5
Allow control of SRC[T/C]5 with assertion of OEB#
0 = Free running, 1 = Stopped with OEB#
4
0
Reserved
Reserved set to 0
3
0
Reserved
Reserved set to 0
2
0
SRC2
Allow control of SRC[T/C]2 with assertion of OEB#
0 = Free running, 1 = Stopped with OEB#
1
0
Reserved
Reserved set to 0
0
Reserved
Reserved set to 0
Byte 4: Control Register 4
Bit
@Pup
Name
Description
7
1
Reserved
Reserved set to 1
6
0
DOT96[T/C]
DOT PWRDWN Drive Mode
0 = Driven in PWRDWN, 1 = Tri-state
5
0
Reserved
Reserved set to 0
4
1
Reserved
Reserved set to 1
3
0
PCIF0
Allow control of PCIF0 with assertion of SW and HW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
2
1
CPU[T/C]2
Allow control of CPU[T/C]2 with assertion of CPU_STP#
0 = Free running, 1 = Stopped with CPU_STP#
1
CPU[T/C]1
Allow control of CPU[T/C]1 with assertion of CPU_STP#
0 = Free running, 1 = Stopped with CPU_STP#
0
1
CPU[T/C]0
Allow control of CPU[T/C]0 with assertion of CPU_STP#
0 = Free running, 1 = Stopped with CPU_STP#
Byte 1: Control Register 1
Bit
@Pup
Name
Description
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