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參數(shù)資料
| 型號： | CY2077ZI-XXX |
| 英文描述： | MISCELLANEOUS CLOCK GENERATOR|TSSOP|8PIN|PLASTIC |
| 中文描述： | 雜項(xiàng)時鐘發(fā)生器| TSSOP封裝| 8引腳|塑料 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 305K |
| 代理商： | CY2077ZI-XXX |
CY2077
6
Output Clock Switching Characteristics Industrial
Over the Operating Range
[3]
Parameter
t
1w
Description
Output Duty Cycle at
1.4V, V
DD
= 4.5–5.5V
t
1w
= t
1A
÷
t
1B
Output Duty Cycle at
V
DD
/2, V
DD
= 4.5–5.5V
t
1x
= t
1A
÷
t
1B
Output Duty Cycle at
V
DD
/2, V
DD
= 3.0–3.6V
t
1y
= t
1A
÷
t
1B
Output Clock Rise Time
Test Conditions
Min.
45
45
45
45
45
45
45
40
Typ.
Max.
55
55
55
55
55
55
55
60
Unit
%
%
%
%
%
%
%
%
1–40 MHz, C
L
<= 35 pF
40–125 MHz, C
L
<= 15 pF
125–133 MHz, C
L
<= 10 pF
1–40 MHz, C
L
<= 35 pF
40–125 MHz, C
L
<= 15 pF
125–133 MHz, C
L
<= 10 pF
1–40 MHz, C
L
<= 20 pF
40–100 MHz, C
L
<= 10 pF
t
1x
t
1y
t
2
Between 0.8 –2.0V, V
DD
= 4.5V–5.5V, C
L
= 35 pF
Between 0.8 –2.0V, V
DD
= 4.5V–5.5V, C
L
= 15 pF
Between 0.8 –2.0V, V
DD
= 4.5V–5.5V, C
L
= 10 pF
Between 0.2V
DD
– 0.8V
DD
, V
DD
= 4.5V–5.5V, C
L
= 35 pF
Between 0.2V
DD
– 0.8V
DD
, V
DD
= 3.0V–3.6V, C
L
= 20 pF
Between 0.2V
DD
– 0.8V
DD
, V
DD
= 3.0V–3.6V, C
L
= 10 pF
Between 0.8V–2.0V, V
DD
= 4.5V–5.5V, C
L
= 35 pF
Between 0.8 –2.0V, V
DD
= 4.5V–5.5V, C
L
= 15 pF
Between 0.8 –2.0V, V
DD
= 4.5V–5.5V, C
L
= 10 pF
Between 0.2V
DD
– 0.8V
DD
, V
DD
= 4.5V-5.5V, C
L
= 35 pF
Between 0.2V
DD
– 0.8V
DD
, V
DD
= 3.0V–3.6V, C
L
= 20 pF
Between 0.2V
DD
– 0.8V
DD
, V
DD
= 3.0V–3.6V, C
L
= 10 pF
PWR_DWN pin LOW to HIGH
[1]
1.8
1.2
0.9
3.4
4.0
2.4
1.8
1.2
0.9
3.4
4.0
2.4
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
t
3
Output Clock Fall Time
t
4
Start-Up Time Out of
Power-Down
Power Down Delay Time
(synchronous setting)
Power Down Delay Time
(asynchronous setting)
Power Up Time
Output Disable Time
(synchronous setting)
Output Disable Time
(asynchronous setting)
Output Enable Time
(always synchronous
enable)
Peak-to-Peak Period
Jitter
1
t
5a
PWR_DWN pin LOW to output LOW
(T=period of output clk)
PWR_DWN pin LOW to output LOW
T/2
T+10
ns
t
5b
10
15
ns
t
6
t
7a
From power on
[1]
OE pin LOW to output Hi-Z
(T=period of output clk)
OE pin LOW to output Hi-Z
1
2
ms
ns
T/2
T+10
t
7b
10
15
ns
t
8
OE pin LOW to HIGH
(T=period of output clk)
T
1.5T+
25ns
ns
t
9
V
DD
=3.0V–3.6V, 4.5V–5.5V, Fo>33 MHz, VCO>100 MHz
V
DD
= 3.0V–5.5V, Fo <33 MHz
80
0.3
%
150
1%
ps
% of
F
O
Switching Waveforms
Duty Cycle Timing
(t
1w,
t
1x,
t
1y
)
t
1A
t
1B
OUTPUT
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