參數(shù)資料
型號: CT1775
廠商: Aeroflex Inc.
英文描述: CT1775 Universal MacAir/1553 Dumb RTU Hybrid
中文描述: CT1775通用MacAir/1553啞RTU的混合
文件頁數(shù): 9/14頁
文件大?。?/td> 184K
代理商: CT1775
9
SCDCT1775 Rev B
PIN FUNCTION AND LOADING TABLE
PIN
#
NAME
I
IH
(μA)
I
IL
(mA)
I
OH
(mA)
I
OL
(mA)
DESCRIPTION
1
GND
Power supply and logic return.
2
+5V OSC/
CLOCK POWER
+5V Power for oscillator and clock driver.
3
NC
No connection.
4
TX INHIBIT
20
-0.4
A LOW on this input inhibits the transmitter.
5
SYNC SELECT
20
-0.4
A LOW on this input results in a transmitted DATA sync. A
HIGH on this input results in a transmitted COMMAND
(or STATUS) sync.
6
SERIAL DATA OUT
-0.4
4.0
Received serial data in NRZ format is available at this
output when TAKE DATA is LOW.
7
ESC OUT
-0.4
4.0
LOW to HIGH transitions on this output when SEND
DATA is HIGH causes the transmit cycle data shifting to
occur.
8
NC
No connection.
9
COMM/DATA SYNC
-.36
3.6
A LOW on this output indicates receipt of a DATA word. A
HIGH indicates receipt of a COMMAND (or STATUS)
word.
10
MRST
40
-0.8
A LOW on this input (1 μsec minimum) resets the
decoderto its initialized condition (same function as DEC
RST), resets FAIL-SAFE, and stops and clears the transmit
cycle. This function interrupts and overridesall
othercontrols.
11
VALID WORD
-0.4
4.0
A LOW on this output indicates receipt of a valid word.
12
BIT STATUS
-0.4
4.0
A LOW on this output, during wrap around self test only,
indicates that the last word decoded was identical to the last
word encoded.
13
LATCH DATA 1
20
-0.4
A HIGH on this input causes parallel tri-state I/O data on
D8 through D15 to appear at the output of the first rank
transmit register. A LOW locks out the register inputs.
14
VAL CMD WD
-0.4
4.0
A LOW on this output indicates the receipt of a valid
command word.
15
BDCST INH
20
-0.4
A LOW on this input inhibits the indication of the
BROADCAST output flag.
16
TMADD1*
20
-0.4
Part of 5 bit hard-wired terminal address input.
17
TMADD3*
20
-0.4
Part of 5 bit herd-wired terminal address input.
18
XTAL
A 12 MHz parallel resonant crystal is connected between
this input and ground.
19
CLOCK OUT
-1.0
1.0
Output of oscillator and clock driver (see text).
20
TAKE DATA
-0.4
4.0
A LOW on this output indicates that received data is being
shifted into the first rank register and is available at
SERIAL DATA OUT. A LOW to HIGH transition transfers
the contents of the first rank receiver register to the second
rank register.
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