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參數(shù)資料
| 型號(hào)： | CS61884-IRZ |
| 廠商： | Cirrus Logic Inc |
| 文件頁(yè)數(shù)： | 35/72頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC LN INTERF T1/E1/J1 160-LFBGA |
| 標(biāo)準(zhǔn)包裝： | 126 |
| 功能： | 線路接口單元（LIU） |
| 接口： | E1，J1，T1 |
| 電路數(shù)： | 8 |
| 電源電壓： | 3.14 V ~ 3.47 V |
| 功率（瓦特）： | 1.73W |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 160-LFBGA |
| 供應(yīng)商設(shè)備封裝： | 160-TFGBA（13x13） |
| 包裝： | 散裝 |
| 包括： | AMI 編碼器和解碼器，B8ZS 編碼器和解碼器，HDB3 編碼器和解碼器，LOS 檢測(cè) |
| 產(chǎn)品目錄頁(yè)面： | 759 (CN2011-ZH PDF) |
| 其它名稱(chēng)： | 598-1717 |
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CS61884
40
DS485F3
14.22 AIS Interrupt Status Register (15h)
14.23 AWG Broadcast Register (16h)
14.24 AWG Phase Address Register (17h)
14.25 AWG Phase Data Register (18h)
14.26 AWG Enable Register (19h)
BIT
NAME
Description
[7:0]
AISI 7-0
Bit n is set to “1” to indicate a change of status of bit n in the AIS Status Register. The bits in
this register indicate which channel changed in status since the last cleared AIS interrupt.
Register bits default to 00h after power-up or reset.
BIT
NAME
Description
[7:0]
AWGB 7-0
Setting bit n to “1” causes the phase data in the AWG Phase Data Register to be written to
the corresponding channel or channels simultaneously. (Refer to Arbitrary Waveform Gen-
erator (See Section 15 on page 43). Register bits default to 00h after power-up or reset.
BIT
NAME
Description
[7:5]
AWGA
These bits specify the target channel 0-7. (Refer to Arbitrary Waveform Generator (See
Section 15 on page 43). Register bits default to 00h after power-up or reset.
[4:0]
PA[4:0]
These bits specify 1 of 24 (E1) or 26/28 (T1/J1) phase sample address locations of the AWG,
that the phase data in the AWG Phase Data Register is written to or read from. The other
locations in each channel’s phase sample addresses are not used, and should not be
accessed. Register bits default to 00h after power-up or reset.
BIT
NAME
Description
[7]
RSVD
RESERVED (This bit must be set to 0.)
[6:0]
AWGD [6:0]
These bits are used for the pulse shape data that will be written to the AWG phase location
specified by the AWG Phase Address Register. The value written to or read from this register
will be written to or read from the AWG phase sample location specified by the AWG Phase
Address register. A software reset through the Software Reset Register does not effect the
contents of this register. The data in each phase is a 7-bit 2’s complement number (the max-
imum positive value is 3Fh and the maximum negative value is 40h). (Refer to Arbitrary
Waveform Generator (See Section 15 on page 43). Register bits default to 00h after
power-up.
BIT
NAME
Description
[7:0]
AWGN 7-0
The AWG enable register is used for selecting the source of the customized transmission
pulse-shape. Setting bit n to “1” in this register selects the AWG as the source of the output
pulse shape for channel n. When bit n is set to “0” the pre-programmed pulse shape in the
ROM is selected for transmission on channel n. (Refer to Arbitrary Waveform Generator
(See Section 15 on page 43). Register bits default to 00h after power-up or reset.
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