參數(shù)資料
型號： CS61881
英文描述： Octal E1 Analog Front EndLine Interface Units
中文描述： 八路素E1模擬前端底線接口單元
文件頁數(shù)： 9/28頁
文件大?。?/td> 461K
代理商： CS61881
CS61881
DS451PP3
9
2. THEORY OF OPERATION
The CS61881 is designed to provide the analog
front end (AFE) for up to eight E1 lines. The device
provides an interface to twisted pair or co-axial me-
dia. A patented matched impedance technique is
employed that reduces power and eliminates the
need for matching resistors. As a result, the device
can interface directly to the line through a trans-
former without the need for matching resistors on
either the receive side or the transmit side.
2.1 Transmitter
The CS61881 contains eight identical transmitters
that each use a low power matched impedance driv-
er to eliminate the need for external load matching
resistors. As a result, the TTIP/TRING outputs can
be direct connected to the pulse transformer allow-
ing one hardware circuit for both 120
and 75
applications (see the
Applications
section). In addi-
tion, the matched impedance driver provides im-
proved return loss when compared to solutions
with external matching resistors. The appropriate
line matching is selected via the CBLSEL control
pin.
The line drivers transmit data received in either
NRZ or RZ format depending on the state of
TCLK. When TCLK is driven with an external
clock, NRZ data sampled on TPOS/TNEG will be
transmitted onto the line via TTIP/TRING. In this
mode, a transmit pulse shape compliant to G.703
will be generated internally (see Figure 4). Data on
TPOS/TNEG is sampled on the falling edge of
TCLK.
If TCLK is held high for at least 12
μ
S, RZ data
driven into TPOS/TNEG is transmitted on
TTIP/TRING. In this mode, the width of positive
pulses is controlled by the width of the pulses on
TPOS and the width of negative pulses is con-
trolled by the width of the pulses on TNEG.
The transmitter can be forced into a high impedance,
low power state by holding TCLK low. Alternately,
the TXOE pin can be used to force all eight trans-
mitters into a high impedance state. This feature is
useful in applications that require redundancy.
2.2 Receiver
The CS61881 contains eight identical receivers that
each use a matched impedance technique that al-
lows a common set of external components for both
120
and 75
operation. This allows one stuffing
option to accommodate both line impedances. The
appropriate line matching is set via the CBLSEL
pin.
The receiver slices the incoming signal on
RTIP/RING and outputs the recovered data on
RPOS/RNEG. To maximize the signal-to-noise ra-
tio, the slicing threshold is dynamically adjusted
based on the amplitude of the incoming signal. In
the absence of a signal, a minimum threshold is
maintained to reduce the occurrence of impulse
noise. The receiver is capable of recovering signals
with over 12 dB of attenuation (referenced to
2.37 V nominal).
269 ns
244 ns
194 ns
219 ns
488 ns
Nominal Pulse
0
10
50
80
90
100
110
120
-10
-20
Percent of
nominal
peak
voltage
Figure 4. Mask of the Pulse at the 2048 kbps Interface
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CS61881-IB 制造商:Rochester Electronics LLC 功能描述:- Bulk
CS61881-IQ 制造商:Rochester Electronics LLC 功能描述:144TQFP - Bulk
CS61884 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:Octal T1/E1/J1 Line Interface Unit
CS61884_05 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:Octal T1/E1/J1 Line Interface Unit
CS61884-IB 功能描述:網(wǎng)絡(luò)控制器與處理器 IC IC Octal T1/E1/J1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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