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參數(shù)資料
| 型號： | CS61881 |
| 英文描述： | Octal E1 Analog Front EndLine Interface Units |
| 中文描述： | 八路素E1模擬前端底線接口單元 |
| 文件頁數(shù)： | 21/28頁 |
| 文件大?。?/td> | 461K |
| 代理商： | CS61881 |
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CS61881
DS451PP3
21
TCLK4 - Transmit Clock Input Port 4, LQFP Pin 107, BGA Pin B14.
TPOS4 - Transmit Positive Pulse Input, LQFP Pin 108, BGA Pin B13.
TNEG4 - Transmit Negative Pulse Input, LQFP Pin 109, BGA Pin B12.
RCLK4 - Receive Clock Output, LQFP Pin 110, BGA Pin A14.
RPOS4 - Receive Positive Pulse Output, LQFP Pin 111, BGA Pin A13.
RNEG4 - Receive Negative Pulse Output, LQFP Pin 112, BGA Pin A12.
TCLK5 - Transmit Clock Input Port 5, LQFP Pin 100, BGA Pin D14
TPOS5 - Transmit Positive Pulse Input, LQFP Pin 101, BGA Pin D13.
TNEG5 - Transmit Negative Pulse Input, LQFP Pin 102, BGA Pin D12.
RCLK5 - Receive Clock Output, LQFP Pin 103, BGA Pin C14.
RPOS5 - Receive Positive Pulse Output, LQFP Pin 104, BGA Pin C13.
RNEG5 - Receive Negative Pulse Output, LQFP Pin 105, BGA Pin C12.
TCLK6 - Transmit Clock Input Port 6, LQFP Pin 9, BGA Pin D1.
TPOS6 - Transmit Positive Pulse Input, LQFP Pin 8, BGA Pin D2.
TNEG6 - Transmit Negative Pulse Input, LQFP Pin 7, BGA Pin D3.
RCLK6 - Receive Clock Output, LQFP Pin 6, BGA Pin C1.
RPOS6 - Receive Positive Pulse Output, LQFP Pin 5, BGA Pin C2.
RNEG6 - Receive Negative Pulse Output, LQFP Pin 4, BGA Pin C3.
TCLK7 - Transmit Clock Input Port 7, LQFP Pin 2, BGA Pin B1.
TPOS7 - Transmit Positive Pulse Input, LQFP Pin 1, BGA Pin B2.
TNEG7 - Transmit Negative Pulse Input, LQFP Pin 144, BGA Pin B3.
RCLK7 - Receive Clock Output, LQFP Pin 143, BGA Pin A1.
RPOS7 - Receive Positive Pulse Output, LQFP Pin 142, BGA Pin A2.
RNEG7 - Receive Negative Pulse Output, LQFP Pin 141, BGA Pin A3.
TTIP0 - Transmit Tip Output, LQFP Pin 45, BGA Pin N5.
TRING0 - Transmit Ring Output, LQFP Pin 46, BGA Pin P5.
These pins are the output of the differential transmit driver. The driver matches impedances for
75
unbalanced and 120
balanced lines requiring only a 1:1.15 transformer. The CBLSEL
pin is used to select the appropriate impedance for line matching.
Note: TTIP and TRING are forced to a high impedance state when the TCLK pin is Low for
over 12
μ
S.
RTIP0 - Receive Tip Input, LQFP Pin 48, BGA Pin P7.
RRING0 - Receive Ring Input, LQFP Pin 49, BGA Pin N7.
The pins are the differential line inputs to the receiver. The receiver internally matches
impedances for 75
unbalanced and 120
balanced lines requiring only a 1:2 transformer,
two external 15
resistors, and one capacitor. The CBLSEL pin is used to select the
appropriate impedance for line matching.
Data recovered from the signal input on these pins is output via RPOS, RNEG, and RCLK.
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相關(guān)代理商/技術(shù)參數(shù) |
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| CS61881-IB | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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| CS61884 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:Octal T1/E1/J1 Line Interface Unit |
| CS61884_05 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:Octal T1/E1/J1 Line Interface Unit |
| CS61884-IB | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC IC Octal T1/E1/J1 Line Interface Unit RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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