參數(shù)資料
型號(hào)： CS5532-BSZ
廠商： Cirrus Logic Inc
文件頁(yè)數(shù)： 26/43頁(yè)
文件大?。?/td> 0K
描述： IC ADC 24BIT 2CH W/LNA 20SSOP
標(biāo)準(zhǔn)包裝： 66
位數(shù)： 24
采樣率（每秒）： 3.84k
數(shù)據(jù)接口： 串行
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 45mW
電壓電源： 模擬和數(shù)字，雙 ±
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 20-SSOP（0.209"，5.30mm 寬）
供應(yīng)商設(shè)備封裝： 20-SSOP
包裝： 管件
輸入數(shù)目和類(lèi)型： 2 個(gè)差分，單極；2 個(gè)差分，雙極
產(chǎn)品目錄頁(yè)面： 755 (CN2011-ZH PDF)
配用： 598-1159-ND - BOARD EVAL FOR CS5532U ADC
其它名稱(chēng)： 598-1113-5
CS5531/32/33/34-AS
32
DS289F5
2.5.6. System Calibration
For the system calibration functions, the user must
supply the converter’s calibration signals which rep-
resent ground and full scale. When a system offset
calibration is performed, a ground-referenced signal
must be applied to the converters. Figure 13 illus-
trates system offset calibration.
As shown in Figure 14, the user must input a signal
representing the positive full-scale point to perform
a system gain calibration. In either case, the cali-
bration signals must be within the specified calibra-
tion limits for each specific calibration step (refer
to the System Calibration Specifications).
2.5.7. Calibration Tips
Calibration steps are performed at the output word
rate selected by the WR2-WR0 bits of the channel
setup registers. Due to limited register lengths in
the faster word-rate filters (240 Sps and higher),
channels that are used at these rates should also be
calibrated in one of these word rates, and channels
used in the lower word rates (120 Sps and lower)
should be calibrated at one of these lower rates.
Since higher word rates result in conversion words
with more peak-to-peak noise, calibration should
be performed at the lowest possible output word
rate for maximum accuracy. For the 7.5 Sps to 120
Sps word rate settings, calibrations can be per-
formed at 7.5 Sps, and for 240 Sps and higher, cal-
ibration can be performed at 240 Sps. To minimize
digital noise near the device, the user should wait
for each calibration step to be completed before
reading or writing to the serial port. Reading the
calibration registers and averaging multiple cali-
brations together can produce a more accurate cal-
ibration result. Note that accessing the ADC’s
serial port before a calibration has finished may re-
sult in the loss of synchronization between the mi-
+
_
AIN+
AIN-
1X GAIN
Figure 11. Self-calibration of Offset
AIN+
AIN-
OPEN
+
-
XGAIN
+
-
OPEN
CLOSED
VREF+
CLOSED
VREF-
+
-
Reference
Figure 12. Self-calibration of Gain
+
-
XGAIN
+
-
External
Connections
0V
+
-
AIN+
AIN-
CM +
-
Figure 13. System Calibration of Offset
+
-
XGAIN
+
-
External
Connections
Full Scale +
-
AIN+
AIN-
CM +
-
Figure 14. System Calibration of Gain
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CS5532-BSZ/H 制造商:Cirrus Logic 功能描述:
CS5532-BSZR 功能描述:模數(shù)轉(zhuǎn)換器 - ADC IC 16-Bit ADCs w/UltraLw Noise PGIA RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
CS5533 制造商:CIRRUS 制造商全稱(chēng):Cirrus Logic 功能描述:16-bit and 24-bit ADCs with Ultra-low-noise PGIA
CS5533-AS 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 4-Ch 16-Bit ADCs w/ Ultra Low Noise PGIA RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
CS5533-ASR 功能描述:模數(shù)轉(zhuǎn)換器 - ADC IC 16-Bit ADCs w/UltraLw Noise PGIA RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
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