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參數(shù)資料
| 型號(hào)： | CS5532-BSZ |
| 廠商： | Cirrus Logic Inc |
| 文件頁(yè)數(shù)： | 24/43頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 24BIT 2CH W/LNA 20SSOP |
| 標(biāo)準(zhǔn)包裝： | 66 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 3.84k |
| 數(shù)據(jù)接口： | 串行 |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 45mW |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-SSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 2 個(gè)差分，單極；2 個(gè)差分，雙極 |
| 產(chǎn)品目錄頁(yè)面： | 755 (CN2011-ZH PDF) |
| 配用： | 598-1159-ND - BOARD EVAL FOR CS5532U ADC |
| 其它名稱： | 598-1113-5 |
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CS5531/32/33/34-AS
30
DS289F5
2.5. Calibration
Calibration is used to set the zero and gain slope of
the ADC’s transfer function. The CS5531/32/33/34
offer both self-calibration and system calibration.
Note:
After the ADCs are reset, they are functional
and can perform measurements without
being calibrated (remember that the VRS bit
in the configuration register must be properly
configured). In this case, the converter will
utilize the initialized values of the on-chip
registers (Gain = 1.0, Offset = 0.0) to
calculate output words. Any initial offset and
gain errors in the internal circuitry of the chip
will remain.
2.5.1. Calibration Registers
The CS5531/32/33/34 converters have an individu-
al offset and gain register for each channel input.
The gain and offset registers, which are used during
both self and system calibration, are used to set the
zero and gain slope of the converter’s transfer func-
tion. As shown in Offset Register section, one LSB
in the offset register is 1.835007966 x 2-24 propor-
tion of the input span (bipolar span is 2 times the
unipolar span, gain register = 1.000...000 decimal).
The MSB in the offset register determines if the
offset to be trimmed is positive or negative (0 pos-
itive, 1 negative). Note that the magnitude of the
offset that is trimmed from the input is mapped
through the gain register. The converter can typi-
cally trim ±100% of the input span. As shown in the
Gain Register section, the gain register spans from
0 to (64 - 2-24). The decimal equivalent meaning of
the gain register is
where the binary numbers have a value of either
zero or one (bD29 is the binary value of bit D29).
While gain register settings of up to 64 - 2-24 are
available, the gain register should never be set to
values above 40.
2.5.2. Gain Register
The gain register span is from 0 to (64-2-24). After Reset D24 is 1, all other bits are ‘0’.
2.5.3. Offset Register
One LSB represents 1.835007966 X 2-24 proportion of the input span (bipolar span is 2 times unipolar span).
Offset and data word bits align by MSB. After reset, all bits are ‘0’.
The offset register is stored as a 32-bit, two’s complement number, where the last 8 bits are all 0.
Db
D29
2
5
b
D28
2
4
b
D27
2
3
… b
D0
2
24
–
)
+++
+
b
Di
2
24
–
i
+
()
i
0
=
29
∑
==
MSB
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
NU
25
24
23
22
21
20
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
000
0000
10000
0000
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
LSB
2-9
2-10
2-11
2-12
2-13
2-14
2-15
2-16
2-17
2-18
2-19
2-20
2-21
222
2-23
2-24
000
0000
00000
0000
MSB
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
Sign
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
2-13
2-14
2-15
2-16
000
0000
00000
0000
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
LSB
2-17
2-18
2-19
2-20
2-21
2-22
2-23
2-24
NU
000
0000
00000
0000
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CS5532-BSZ/H | 制造商:Cirrus Logic 功能描述: |
| CS5532-BSZR | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC IC 16-Bit ADCs w/UltraLw Noise PGIA RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| CS5533 | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:16-bit and 24-bit ADCs with Ultra-low-noise PGIA |
| CS5533-AS | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 4-Ch 16-Bit ADCs w/ Ultra Low Noise PGIA RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| CS5533-ASR | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC IC 16-Bit ADCs w/UltraLw Noise PGIA RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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