參數(shù)資料
型號(hào): CS5532-BSZ
廠商: Cirrus Logic Inc
文件頁(yè)數(shù): 15/43頁(yè)
文件大?。?/td> 0K
描述: IC ADC 24BIT 2CH W/LNA 20SSOP
標(biāo)準(zhǔn)包裝: 66
位數(shù): 24
采樣率(每秒): 3.84k
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 45mW
電壓電源: 模擬和數(shù)字,雙 ±
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-SSOP(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: 20-SSOP
包裝: 管件
輸入數(shù)目和類型: 2 個(gè)差分,單極;2 個(gè)差分,雙極
產(chǎn)品目錄頁(yè)面: 755 (CN2011-ZH PDF)
配用: 598-1159-ND - BOARD EVAL FOR CS5532U ADC
其它名稱: 598-1113-5
CS5531/32/33/34-AS
22
DS289F5
2.2.4. Serial Port Interface
The CS5531/32/33/34’s serial interface consists of
four control lines: CS, SDI, SDO, SCLK. Figure 7
details the command and data word timing.
CS, Chip Select, is the control line which enables
access to the serial port. If the CS pin is tied low,
the port can function as a three-wire interface.
SDI, Serial Data In, is the data signal used to trans-
fer data to the converters.
SDO, Serial Data Out, is the data signal used to
transfer output data from the converters. The SDO
output will be held at high impedance any time CS
is at logic 1.
SCLK, Serial Clock, is the serial bit-clock which
controls the shifting of data to or from the ADC’s
serial port. The CS pin must be held low (logic 0)
before SCLK transitions can be recognized by the
port logic. To accommodate optoisolators SCLK is
designed with a Schmitt-trigger input to allow an
optoisolator with slower rise and fall times to di-
rectly drive the pin. Additionally, SDO is capable
of sinking or sourcing up to 5 mA to directly drive
an optoisolator LED. SDO will have less than a 400
mV loss in the drive voltage when sinking or sourc-
ing 5 mA.
Command Time
8SCLKs
Data Time 32 SCLKs
Write Cycle
CS
SCLK
SDI
MSB
Command Time
8SCLKs
CS
SCLK
SDI
Read Cycle
SDO
MSB
LSB
Command Time
8SCLKs
8 SCLKs Clear SDO Flag
SDO
SCLK
SDI
MSB
LSB
Clock Cycles
t*
d
CS
Data Time 32 SCLKs
LSB
Data Conversion Cycle
/OWR
MCLK
* td is the time it takes the ADC to perform a conversion. See the Single
Conversion and Continuous Conversion sections of the data sheet for more
details about conversion timing.
Figure 7. Command and Data Word Timing
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CS5532-BSZ/H 制造商:Cirrus Logic 功能描述:
CS5532-BSZR 功能描述:模數(shù)轉(zhuǎn)換器 - ADC IC 16-Bit ADCs w/UltraLw Noise PGIA RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
CS5533 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:16-bit and 24-bit ADCs with Ultra-low-noise PGIA
CS5533-AS 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 4-Ch 16-Bit ADCs w/ Ultra Low Noise PGIA RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
CS5533-ASR 功能描述:模數(shù)轉(zhuǎn)換器 - ADC IC 16-Bit ADCs w/UltraLw Noise PGIA RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32