參數(shù)資料
型號(hào): CS5371A-ISZ
廠商: Cirrus Logic Inc
文件頁數(shù): 17/32頁
文件大?。?/td> 0K
描述: IC MODULATOR LP/HP 1CH 24-SSOP
標(biāo)準(zhǔn)包裝: 59
類型: 調(diào)制器
分辨率(位): 24 b
采樣率(每秒): 512k
電壓電源: 模擬和數(shù)字
電源電壓: ±2.5V,3.3 V ~ 5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-SSOP(0.209",5.30mm 寬)
供應(yīng)商設(shè)備封裝: 24-SSOP
包裝: 管件
配用: 598-1778-ND - EVALUATION BOARD FOR CS5376
CS5371A CS5372A
24
DS748F3
8.4 SCR Latch-up Considerations
It is recommended to connect the VA- power
supply to system ground (GND) with a re-
verse-biased Schottky diode. At power up, if
the VA+ power supply ramps up before the
VA- supply is established, the VA- pin voltage
could be pulled above ground potential
through the CS5371A and CS5372A device. If
the VA- supply is pulled 0.7 V or more above
GND, SCR latch-up can occur. A reverse-bi-
ased Schottky diode will clamp the VA- voltage
a maximum of 0.3 V above ground to ensure
SCR latch-up does not occur at power up.
8.5 DC-DC Converters
Many low-frequency measurement systems
are battery powered and utilize DC-DC con-
verters to efficiently generate power supply
voltages. To minimize interference effects, op-
erate the DC-DC converter at a frequency
which is rejected by the digital filter, or operate
it synchronous to the MCLK rate.
A synchronous DC-DC converter whose oper-
ating frequency is derived from MCLK will the-
oretically minimize the potential for “beat
frequencies” to appear in the measurement
bandwidth. However this requires the source
clock to remain jitter free within the DC-DC
converter circuitry. If clock jitter can occur with-
in the DC-DC converter (as in a PLL-based ar-
chitecture),
it’s
better
to
use
a
non-
synchronous DC-DC converter whose switch-
ing frequency is rejected by the digital filter.
During PCB layout, do not place high-current
DC-DC converters near sensitive analog com-
ponents. Carefully routing a separate DC-DC
“star” ground will help isolate noisy switching
currents away from the sensitive analog com-
ponents.
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