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參數(shù)資料
| 型號(hào)： | CS4299-JQZ |
| 廠商： | Cirrus Logic Inc |
| 文件頁數(shù)： | 27/52頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CODEC AC 97 W/SRC 48LQFP |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 系列： | SoundFusion™ |
| 類型： | 音頻編解碼器 '97 |
| 數(shù)據(jù)接口： | 串行 |
| 分辨率（位）： | 18 b，20 b |
| ADC / DAC 數(shù)量： | 1 / 1 |
| 三角積分調(diào)變： | 是 |
| 動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db)： | 85 / 87 |
| 電壓 - 電源，模擬： | 4.75 V ~ 5.25 V |
| 電壓 - 電源，數(shù)字： | 4.75 V ~ 5.25 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 754 (CN2011-ZH PDF) |
| 其它名稱： | 598-1044 |
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CS4299
33
5. POWER MANAGEMENT
5.1
AC ’97 Reset Modes
The CS4299 supports three reset methods, as de-
fined in the AC ’97 Specification: Cold AC ’97 Re-
set, Warm AC ’97 Reset, Register AC ’97 Reset. A
Cold Reset results in all AC ’97 logic (registers in-
cluded) initialized to its default state. A Warm Re-
set leaves the contents of the AC ’97 register set
unaltered. A Register Reset initializes only the
AC ’97 registers to their default states.
5.1.1
Cold AC ‘97 Reset
A Cold Reset is achieved by asserting RESET# for
a minimum of 1 s after the power supply rails
have stabilized. This is done in accordance with the
minimum timing specifications in the AC ’97 Seri-
al Port Timing section on page 7. Once deasserted,
all of the CS4299 registers will be reset to their de-
fault power-on states and the BIT_CLK and
SDATA_IN signals will be reactivated.
5.1.2
Warm AC ’97 Reset
A Warm Reset allows the AC-link to be reactivated
without losing information in the CS4299 registers.
A Warm Reset is required to resume from a D3hot
state, where the AC-link had been halted yet full
power had been maintained. A primary codec
Warm Reset is initiated when the SYNC signal is
driven high for at least 1 s and then driven low in
the absence of the BIT_CLK clock signal. The
BIT_CLK clock will not restart until at least 2 nor-
mal BIT_CLK clock periods (162.8 ns) after the
SYNC signal is deasserted. A Warm Reset of the
secondary codec is recognized when the primary
codec on the AC-link resumes BIT_CLK genera-
tion. The CS4299 will wait for BIT_CLK to be sta-
ble to restore SDATA_IN activity and/or S/PDIF
transmission on the following frame.
5.1.3
Register AC ’97 Reset
The third reset mode provides a Register Reset to
the CS4299. This is available only when the
CS4299 AC-link is active and the Codec Ready bit
is ‘set’. The audio (including extended audio) reg-
isters (Index 00h - 38h) and the vendor specific reg-
isters (Index 5Ah - 7Ah) are reset to their default
states by a write of any value to the Reset Register
(Index 00h).
DS319PP6
33
CS4299
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CS4299-JQZ | 制造商:Cirrus Logic 功能描述:A/D Converter (A-D) IC |
| CS4299-JQZ | 制造商:Cirrus Logic 功能描述:IC AUDIO CODEC 2CH AC97 W/HA |
| CS4299-JQZR | 功能描述:接口—CODEC IC AC’97 Codec w/SRC RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| CS4299-KQ | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:CrystalClear SoundFusion Audio Codec 97 |
| CS4299-KQZ | 制造商:CIRRUS 制造商全稱:Cirrus Logic 功能描述:CrystalClear SoundFusion Audio Codec 97 |
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