4.13 Powerdown Control/Status Register (Index 26h) EAPD External Amplifier Power Down. The EAPD pin follows this bit and is ge" />
參數(shù)資料
型號(hào)： CS4299-JQZ
廠商： Cirrus Logic Inc
文件頁(yè)數(shù)： 20/52頁(yè)
文件大?。?/td> 0K
描述： IC CODEC AC 97 W/SRC 48LQFP
標(biāo)準(zhǔn)包裝： 250
系列： SoundFusion™
類(lèi)型： 音頻編解碼器 '97
數(shù)據(jù)接口： 串行
分辨率（位）： 18 b，20 b
ADC / DAC 數(shù)量： 1 / 1
三角積分調(diào)變： 是
動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db)： 85 / 87
電壓 - 電源，模擬： 4.75 V ~ 5.25 V
電壓 - 電源，數(shù)字： 4.75 V ~ 5.25 V
工作溫度： 0°C ~ 70°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP（7x7）
包裝： 管件
產(chǎn)品目錄頁(yè)面： 754 (CN2011-ZH PDF)
其它名稱(chēng)： 598-1044
CS4299
27
4.13
Powerdown Control/Status Register (Index 26h)
EAPD
External Amplifier Power Down. The EAPD pin follows this bit and is generally used to power
down external amplifiers.
PR6
Alternate Line Out Powerdown. When ‘set’, the alternate line out buffer is powered down.
PR5
Internal Clock Disable. When ‘set’, this bit completely powers down both the analog and digital
sections of the CS4299. The only way to recover from setting this bit is through a Cold Reset
(driving the RESET# signal active).
PR4
AC-link Powerdown. When ‘set’, the AC link is powered down (BIT_CLK off). The AC-link can
be restarted through a Warm Reset using the SYNC signal, or a Cold Reset using the RESET#
signal (primary audio codec only).
PR3
Analog Mixer Powerdown (Vref off). When ‘set’, the analog mixer and voltage reference are
powered down. When clearing this bit, the ANL, ADC, and DAC bits should be checked before
writing any mixer registers.
PR2
Analog Mixer Powerdown (Vref on). When ‘set’, the analog mixer is powered down (the voltage
reference is still active). When clearing this bit, the ANL bit should be checked before writing
any mixer registers.
PR1
Front DACs Powerdown. When ‘set’, the DACs are powered down. When clearing this bit, the
DAC bit should be checked before sending any data to the DACs.
PR0
L/R ADCs and Input Mux Powerdown. When ‘set’, the ADCs and the ADC input muxes are pow-
ered down. When clearing this bit, no valid data will be sent down the AC link until the ADC bit
goes high.
REF
Voltage Reference Ready Status. When ‘set’, indicates the voltage reference is at a nominal
level.
ANL
Analog Ready Status. When ‘set’, the analog output mixer, input multiplexer, and volume con-
trols are ready. When clear, no volume control registers should be written.
DAC
Front DAC Ready Status. When ‘set’, the DACs are ready to receive data across the AC link.
When clear, the DACs will not accept any valid data.
ADC
L/R ADC Ready Status. When ‘set’, the ADCs are ready to send data across the AC link. When
clear, no data will be sent to the Controller.
Default
0000h. This value indicates all blocks are powered on. The lower four bits will change as the
CS4299 finishes an initialization and calibration sequence.
The PR[6:0] and the EAPD bits are powerdown control for different sections of the CS4299 as well as external am-
plifiers. The REF, ANL, DAC, and ADC bits are read-only status bits which, when ‘set’, indicate that a particular sec-
tion of the CS4299 is ready. After the controller receives the Codec Ready bit in input Slot 0, these status bits must
be checked before writing to any mixer registers. See Section 5, Power Management, for more information on the
powerdown functions.
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
EAPD
PR6
PR5
PR4
PR3
PR2
PR1
PR0
0
REF
ANL
DAC
ADC
DS319PP6
27
CS4299
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參數(shù)描述
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