5.17 Audio Sample Rate Control Registers (Index 2Ch - 34h) SR[15:0] Sample Rate Select. The Audio Sample Rate Control" />
參數(shù)資料
型號： CS4205-KQZ
廠商： Cirrus Logic Inc
文件頁數(shù)： 32/81頁
文件大?。?/td> 0K
描述： IC CODEC AC97 I2S 48-LQFP
標準包裝： 250
類型： 音頻編解碼器 '97
數(shù)據(jù)接口： 串行
分辨率（位）： 18，20 b
ADC / DAC 數(shù)量： 1 / 2
三角積分調(diào)變： 是
動態(tài)范圍，標準 ADC / DAC (db)： 90 / 90
電壓 - 電源，模擬： 4.75 V ~ 5.25 V
電壓 - 電源，數(shù)字： 4.75 V ~ 5.25 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-TQFP（9x9）
包裝： 托盤
產(chǎn)品目錄頁面： 754 (CN2011-ZH PDF)
其它名稱： 598-1182
CS4205
38
DS489PP4
5.17
Audio Sample Rate Control Registers (Index 2Ch - 34h)
SR[15:0]
Sample Rate Select. The Audio Sample Rate Control Registers (Index 2Ch - 34h) control
playback and capture sample rates. The PCM Front DAC Rate Register (Index 2Ch) controls
the Front Left and Front Right DAC sample rates. The PCM L/R ADC Rate Register
(Index 32h) controls the Left and Right ADC sample rates. The Mic ADC Rate Register (Index
34h) controls the Microphone ADC sample rate. There are ten sample rates directly support-
ed by this register, shown in Table 12. Any value written to this register not contained in
Table 12 is not directly supported and will be decoded according to the ranges indicated in
the table. The range boundaries have been chosen so that only bits SR[15:11] of each regis-
ter will have to be considered. All register read transactions will reflect the actual value stored
(column 2 in Table 12) and not the one attempted to be written.
Default
BB80h. This value corresponds to 48 kHz sample rate.
Writes to the PCM Front DAC Rate Register (Index 2Ch) and the PCM L/R ADC Rate Register (Index 32h) are only
available in Variable Rate PCM Audio mode when the VRA bit in the Extended Audio Status/Control Register
(Index 2Ah) is ‘set’. If VRA = 0, writes to the register are ignored and the register will always read BB80h. Writes to
the Mic ADC Rate Register (Index 34h) are only available in Variable Rate Mic Audio mode when the VRM bit in the
Extended Audio Status/Control Register (Index 2Ah) is ‘set’. If VRM = 0, writes to the register are ignored and the
register will always read BB80h. Table 11 lists the SRC registers and their corresponding SRC enable bit.
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SR15
SR14
SR13
SR12
SR11
SR10
SR9
SR8
SR7
SR6
SR5
SR4
SR3
SR2
SR1
SR0
Register
Index
SRC
SRC Enable Bit
(Index 2Ah)
2Ch
PCM Front DAC Rate
VRA
32h
PCM L/R ADC Rate
VRA
34h
Mic ADC Rate
VRM
Table 11. Audio Sample Rate Control Register Index
Sample Rate
(Hz)
SR[15:0], register
content (hex value)
SR[15:0], decode
range (hex value)
SR[15:11], decode
range (bin value)
8,000
1F40
0000 - 1FFF
00000 - 00011
9,600
2580
2000 - 27FF
00100 - 00100
11,025
2B11
2800 - 2FFF
00101 - 00101
13,714
3592
3000 - 37FF
00110 - 00110
16,000
3E80
3800 - 47FF
00111 - 01000
22,050
5622
4800 - 57FF
01001 - 01010
24,000
5DC0
5800 - 6FFF
01011 - 01101
32,000
7D00
7000 - 8FFF
01110 - 10001
44,100
AC44
9000 - AFFF
10010 - 10101
48,000
BB80
B000 - FFFF
10110 - 11111
Table 12. Directly Supported SRC Sample Rates for the CS4205
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