參數(shù)資料
型號(hào): COP8CCR9KMT8
廠商: National Semiconductor
文件頁(yè)數(shù): 74/111頁(yè)
文件大?。?/td> 0K
描述: IC MCU EEPROM 8BIT 32K 56-TSSOP
標(biāo)準(zhǔn)包裝: 34
系列: COP8™ 8C
核心處理器: COP8
芯體尺寸: 8-位
速度: 20MHz
連通性: Microwire/Plus(SPI),UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 49
程序存儲(chǔ)器容量: 32KB(32K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 56-TFSOP(0.240",6.10mm 寬)
包裝: 管件
其它名稱: *COP8CCR9KMT8
SNOS535I – OCTOBER 2000 – REVISED MARCH 2013
5.13.7 BAUD CLOCK GENERATION
The clock inputs to the transmitter and receiver sections of the USART can be individually selected to
come either from an external source at the CKX pin (port L, pin L1) or from a source selected in the PSR
and BAUD registers. Internally, the basic baud clock is created from the MCLK through a two-stage divider
chain consisting of a 1-16 (increments of 0.5) prescaler and an 11-bit binary counter (Figure 5-18). The
divide factors are specified through two read/write registers shown in Figure 5-19. Note that the 11-bit
Baud Rate Divisor spills over into the Prescaler Select Register (PSR). PSR is cleared upon reset.
As shown in Table 5-17, a Prescaler Factor of 0 corresponds to NO CLOCK. This condition is the USART
power down mode where the USART clock is turned off for power saving purpose. The user must also
turn the USART clock off when a different baud rate is chosen.
The correspondences between the 5-bit Prescaler Select and Prescaler factors are shown in Table 5-17.
There are many ways to calculate the two divisor factors, but one particularly effective method would be to
achieve a 1.8432 MHz frequency coming out of the first stage. The 1.8432 MHz prescaler output is then
used to drive the software programmable baud rate counter to create a 16x clock for the following baud
rates: 110, 134.5, 150, 300, 600, 1200, 1800, 2400, 3600, 4800, 7200, 9600, 19200 and 38400 (Table 5-
16). Other baud rates may be created by using appropriate divisors. The 16x clock is then divided by 16 to
provide the rate for the serial shift registers of the transmitter and receiver.
Table 5-16. Baud Rate Divisors
(1.8432 MHz Prescaler Output)(1)
Baud Rate
Divisor
1 (N-1)
110 (110.03)
1046
134.5 (134.58)
855
150
767
300
383
600
191
1200
95
1800
63
2400
47
3600
31
4800
23
7200
15
9600
11
19200
5
38400
2
(1)
The entries in Table 5-16 assume a prescaler output of 1.8432 MHz.
In asynchronous mode the baud rate could be as high as 1250k.
Figure 5-18. USART BAUD Clock Generation
Copyright 2000–2013, Texas Instruments Incorporated
Functional Description
65
Product Folder Links: COP8CBR9 COP8CCR9 COP8CDR9
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