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參數(shù)資料
| 型號： | CH7012 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Chrontel CH7012 TV Output Device |
| 中文描述： | 昆泰CH7012電視輸出設備 |
| 文件頁數(shù)： | 30/42頁 |
| 文件大?。?/td> | 551K |
| 代理商： | CH7012 |
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CHRONTEL
TV PLL M Value Register
CH7012A
PLLM
30
201-0000-042 Rev. 1.1, 9/29/2000
Symbol:
Address:
0Ah
Bits:
8
Register PLLM controls the division factor applied to the 14.31818MHz frequency reference clock before it is input
to the TV PLL phase detector when the CH7012 is operating in master clock mode. The entire bit field, M[8:0], is
comprised of this register M[7:0] plus the MSB value contained in the TV PLL Control register, bit M8. In slave
clock mode, an external pixel clock is used instead of the 14.31818MHz frequency reference, and the division factor
is determined by the XCM value in register 1Dh. A table of values versus display mode is given following the
PLLN register description.
TV PLL N Value Register
Symbol:
PLLN
Address:
0Bh
Bits:
8
Register PLLN controls the division factor applied to the VCO output before being applied to the PLL phase
detector, when the CH7012 is operating in master clock mode. The entire bit field, N[9:0], is comprised of this
register N[7:0] plus the MSB values contained in the TV PLL Control register, bits N9 and N8. In slave clock mode,
the value of ‘N’ is internally set to 1. The pixel clock generated in master clock modes is calculated according to the
equation Fpixel = Fref * [(N+2) / (M+2)]. When using a 14.31818MHz frequency reference, the required M and N
values for each mode are shown in
Table 16
below:
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
TYPE:
DEFAULT:
M7
R/W
M6
R/W
M5
R/W
M4
R/W
M3
R/W
M2
R/W
M1
R/W
M0
R/W
0
0
1
1
1
1
1
1
BIT:
7
6
5
4
3
2
1
0
SYMBOL:
TYPE:
DEFAULT:
N7
N6
N5
N4
N3
N2
N1
N0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
1
1
1
1
1
1
0
Table 16: TV PLL M and N values vs Display Mode
Mode
VGA Resolution,
TV Standard,
Scaling Ratio
512x384, PAL, 5:4
512x384, PAL, 1:1
512x384, NTSC, 5:4
512x384, NTSC, 1:1
720x400, PAL, 5:4
720x400, PAL, 1:1
720x400, NTSC, 5:4
720x400, NTSC, 1:1
640x400, PAL, 5:4
640x400, PAL, 1:1
640x400, NTSC, 5:4
640x400, NTSC, 1:1
640x400, NTSC, 7:8
640x480, PAL, 5:4
640x480, PAL, 1:1
640x480, PAL, 5:6
640x480, NTSC, 1:1
N
10-
bits
20
9
126
110
53
86
106
70
108
9
94
62
190
20
9
9
110
M
9-bits
Mode
VGA Resolution,
TV Standard,
Scaling Ratio
720x480, NTSC, 7:8
720x480, NTSC, 5:6
720x480, PAL, 1:1
720x480, PAL, 5:6
720x480, PAL, 5:7
800x600, PAL, 1:1
800x600, PAL, 5:6
800x600, PAL, 5:7
800x600, NTSC, 3:4
800x600, NTSC, 7:10
800x600, NTSC, 5/8
1024x768, PAL, 5:7
1024x768, PAL, 5:8
1024x768, PAL, 5:9
1024x768, NTSC, 5:8
1024x768, NTSC, 5:9
1024x768, NTSC, 1:2
N
10-
bits
142
214
75
31
9
647
86
42
62
302
126
75
42
20
565
333
917
M
9-bits
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
13
4
89
63
26
33
63
33
61
3
63
33
89
13
4
3
63
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
63
89
38
12
2
313
33
13
19
89
33
16
7
2
137
71
177
相關PDF資料 |
PDF描述 |
|---|---|
| CH7012A | Chrontel CH7012 TV Output Device |
| CH7012A-T | Chrontel CH7012 TV Output Device |
| CH7202 | MPEG to TV Encoder with 8-bit Input |
| CH7203 | MPEG to TV Encoder with 16-bit Input |
| CH7203-V | MPEG to TV Encoder with 16-bit Input |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CH7012A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Chrontel CH7012 TV Output Device |
| CH7012A-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Chrontel CH7012 TV Output Device |
| CH7013A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital PC to TV Encoder |
| CH7013A-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital PC to TV Encoder |
| CH7013A-V | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital PC to TV Encoder |
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