
CHRONTEL
Register Control
The CH7012 is controlled via an serial port control. The serial port bus uses only the SC clock to latch data
into registers, and does not use any internally generated clocks so that the device can be written to in all power
down modes. The device retains all register states.
CH7012A
20
201-0000-042 Rev. 1.1, 9/29/2000
The CH7012 contains a total of 37 registers for user control. A listing of non-Macrovision control bits are
listed below with a brief description of each.
Non-Macrovision Control Registers Map
The non-Macrovision controls are listed below, divided into three sections: general controls, input / output
controls and VGA to TV controls. A register map and register description follows.
GENERAL CONTROLS
ResetIB
ResetDB
PD[5:0]
VID[7:0]
DID[7:0]
TSTP[1:0]
Software
serial port
reset
Software datapath reset
Power down controls (TVD, DACPD[3:0], Full, Partial)
Version ID register
Device ID register
Enable/select test pattern generation (color bar, ramp)
INPUT/OUTPUT CONTROLS
XCM
XCMD[7:0]
MCP
PCM
POUTP
POUTE
HPIE, HPIE2
HPIR
IDF[2:0]
IBS
DES
SYO
XCLK 1X, 2X select
Delay adjust between XCLK and D[11:0]
XCLK polarity control
P-OUT 1X, 2X select
P-OUT clock polarity
P-OUT enable
Hot plug detect interrupt enable
Hot plug detect interrupt reset
Input data format
Input buffer select
Decode embedded sync (TV-Out data only)
H/V sync direction control (for TV-Out modes only)
V sync polarity control (sync polarity to TMDS
TM
links is not changed)
H sync polarity control (sync polarity to TMDS
TM
links is not changed)
Termination detect/check (TMDS
TM
Link, DACT3, DACT2, DACT1, DACT0, SENSE)
Enable BCO Output
Select output signal for BCO pin
BCO polarity
Read or write level for GPIO pins
Direction control for GPIO pins
Enables/selects sync output for Scart and bypass modes
DAC gain control
DAC bypass
Crystal oscillator adjustments
VSP
HSP
TERM[5:0]
BCOEN
BCO[2:0]
BCOP
GPIOL[1:0]
GOENB[1:0]
SYNCO[1:0]
DACG[1:0]
DACBP
XOSC[2:0]