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參數(shù)資料
| 型號(hào)： | BU5071 |
| 文件頁(yè)數(shù)： | 9/30頁(yè) |
| 文件大?。?/td> | 393K |
| 代理商： | BU5071 |
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This mode providesanother stageof path verifica-
tion by enabling datawritten into the Receive PCM
Register to be read back from that register in any
Transmit time-slot at D
X
0 or D
X
1.
For Analog Loopback as well as for Digital Loop-
back PCM decoding continues and analog output
appears at VF
R
O. The output can be disabled by
pro gramming ”No Output” in the Receive Gain
Register(see table 8).
INTERFACELATCH DIRECTIONS
Immediately following power-on, all Interface
Latchesassume they are inputs,and thereforeall
IL pins are in a high impedance state. Each IL pin
may be individuallyprogrammedas alogic input or
output by writing the appropriateinstruction to the
LDR, see table 1 and 4. Bits L
5
-L
0
mustbe set by
writing the specific instruction to the LDR with the
L bits in the secondbyte setasspecifiedin table4.
Unused interface latches should be programmed
as outputs. For the TS5071, L5 should always be
programmedas an output.
Table4:
Byte2 Functionof LatchDirection Register
(*) State at power-on initilization.
Note:
L5 should beprogrammed as an output for the TS5071.
INTERFACE LATCH STATES
Interface Latches configured as outputs assume
the state determined by theappropriate data bit in
the 2-byte instruction written to the Latch Content
Register (ILR) as shown in tables 1 and 5.
Latches configured as inputs will sense the state
applied by an external source, such as the Off-
Hook detect output of a SLIC. All bits of the ILR,
i.e. sensed inputs and the programmed state of
outputs, can be read back in the 2nd byte of a
READ from the ILR. It is recommended that, dur-
ing initialization, the state of IL pins to be config-
ured as outputs should first be programmed, fol-
lowed
immediately
by
Register.
the
Latch
Direction
TIME-SLOT ASSIGNMENT
COMBO IIG can operatein either fixedtime-slot or
time-slotassignmentmodefor selectingtheTrans-
mit and Receive PCM time-slots. Followingpower-
on,thedeviceis automaticallyin Non-DelayedTim-
ingmode,in whichthetime-slot alwaysbeginswith
the leading(rising) edge of frame sync inputs FS
X
and FS
R
. Time-Slot Assignment may onlybe used
with Delayed Data timing : see figure 6. FS
X
and
FS
R
may have any phase relationship with each
otherin BCLK periodincrements.
Bit Number
7
6
5
4
3
2
1
0
L0
L1
L2
L3
L4
L5
X
X
L
N
Bit
IL Direction
Input
*
Output
0
1
Bit Number
Function
7
EN
6
PS
(note 1)
5
T5
(note 2)
4
T4
3
T3
2
T2
1
T1
0
T0
0
X
X
X
X
X
X
X
Disable D
X
Outputs (transmit instruction) *
Disable D
R
Inputs (receive instruction) *
1
0
Assign One Binary Coded Time-slot from 0–63
Assign One Binary Coded Time-slot from 0–63
Enable D
X
0 Output, Disable D
X
1 Output
(Transmit instruction)
Enable D
R
0 Input, Disable D
R
1 Input
(Receive Instruction)
1
1
Assign One Binary Coded Time-slot from 0–63
Assign One Binary Coded Time-slot from 0–63
Enable D
X
1 Output, Disable D
X
0 Output
(Transmit instruction)
Enable D
R
1 Input, Disable D
R
0 Input
(Receive Instruction)
Table 6:
Byte 2 of Time-slotand Port AssignmentInstructions
Bit Number
7
6
5
4
3
2
1
0
D0
D1
D2
D3
D4
D5
X
X
Table 5:
InterfaceLatch Data Bit Order
Notes:
1. The ”PS” bit MUST always be set to 0 for the TS5071.
2. T5 is the MSB of the time-slot assignment.
(*) State at power-on initialization
TS5070 - TS5071
9/30
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