參數(shù)資料
型號: BU5071
文件頁數(shù): 3/30頁
文件大?。?/td> 393K
代理商: BU5071
PIN CONNECTIONS
POWERSUPPLY, CLOCK
Name
Pin
Type
TS5070
FN
TS5071
N
Function
Description
V
CC
V
SS
GND
S
S
S
27
3
1
19
3
1
Positive Power
Supply
Negative
Power Supply
Ground
+ 5 V
±
5 %
– 5 V
±
5 %
All analog and digital signals are referenced to this pin.
BCLK
I
16
12
Bit Clock
Bit clock input used to shift PCM data intoand out of the
D
R
andD
X
pins.BCLK may vary from 64 kHz to 4.096
MHz in 8 kHz increments, and must be synchronous with
MCLK (TS5071 only).
MCLK
I
17
12
Master Clock
Master clock input used by the switched capacitor filters
and theencoder and decoder sequencing logic. Must be
512 kHz, 1. 536/1. 544 MHz,
2.048 MHz or 4.096 MHz and synchronous withBCLK.
BCLK and MCLK are wired together in the TS5071.
PLCC28
TS5070FN
DIP20
TS5071N
TS5070 - TS5071
3/30
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