參數(shù)資料
型號(hào)： BQ3285LDSSTRG4
廠商： TEXAS INSTRUMENTS INC
元件分類： XO, clock
英文描述： REAL TIME CLOCK, PDSO24
封裝： 0.150 INCH, GREEN, PLASTIC, SSOP-24
文件頁(yè)數(shù)： 26/27頁(yè)
文件大小： 170K
代理商： BQ3285LDSSTRG4
other pattern to these bits keeps the oscillator off. A
pattern of 010 must be set for the bq3285ED/LD to keep
time in battery backup mode.
Power-Down/Power-Up Cycle
The bq3285ED and bq3285LD power-up/power-down cy-
cles are different. The bq3285LD continuously monitors
VCC for out-of-tolerance. During a power failure, when
VCC falls below VPFD (2.53V typical), the bq3285LD write-
protects the clock and storage registers. The power source
is switched to BC when VCC is less than VPFD and BC is
greater than VPFD, or when VCC is less than VBC and VBC
is less than VPFD. RTC operation and storage data are
sustained by a valid backup energy source. When VCC is
above VPFD, the power source is VCC. Write-protection con-
tinues for tCSR time after VCC rises above VPFD.
The bq3285ED continuously monitors VCC for out-of-
tolerance. During a power failure, when VCC falls below
VPFD (4.17V typical), the bq3285ED write-protects the
clock and storage registers. When VCC is below VBC (3V
typical), the power source is switched to BC. RTC opera-
tion and storage data are sustained by a valid backup
energy source.
When VCC is above VBC, the power
source is VCC. Write-protection continues for tCSR time
after VCC rises above VPFD.
Control/Status Registers
The four control/status registers of the bq3285ED/LD
are accessible regardless of the status of the update cy-
cle (see Table 4).
Register A
Register A programs:
n
The frequency of the periodic event rate.
n
Oscillator operation.
n
Time-keeping
Register A provides:
n
Status of the update cycle.
RS0–RS3 - Frequency Select
These bits select the periodic interrupt rate, as shown in
Table 3.
OS0–OS2 - Oscillator Control
These three bits control the state of the oscillator and
divider stages. A pattern of 010 or 011 enables RTC op-
eration by turning on the oscillator and enabling the fre-
quency divider. This pattern must be set to turn the os-
cillator on and to ensure that the bq3285ED/LD keeps
time in battery-backup mode. A pattern of 11X turns the
oscillator on, but keeps the frequency divider disabled.
When 010 is written, the RTC begins its first update af-
ter 500ms.
8
bq3285ED/LD
Register A Bits
76543210
UIP
OS2
OS1
OS0
RS3
RS2
RS1
RS0
76543210
----
RS3
RS2
RS1
RS0
76543210
-
OS2
OS1
OS0
----
July 1997
Reg.
Loc.
(Hex) Read Write
Bit Name and State on Reset
7 (MSB)
6
5
4
3
2
1
0 (LSB)
A
0A
Yes
1
UIP
na
OS2
na
OS1
na
OS0 na
RS3
na
RS2
na
RS1
na
RS0
na
B
0B
Yes
UTI
na
PIE
0
AIE
0
UIE
0
-
0
DF
na
HF
na
DSE na
C
0C
Yes
No
INTF
0
PF
0
AF
0
UF
0
-
0
-
na
-
0
-
0
D
0D
Yes
2
VRT
na
-
0
DA5 na DA4 na
DA3
na DA2 na DA1 na
DA0 na
Notes:
na = not affected.
1.
Except bit 7.
2.
Except bits 6 and 7.
Table 4. Control/Status Registers
相關(guān)PDF資料
PDF描述
BQ3285LDSS 0 TIMER(S), REAL TIME CLOCK, PDSO24
BQ3285EDSS 0 TIMER(S), REAL TIME CLOCK, PDSO24
BQ3285LSS 1 TIMER(S), REAL TIME CLOCK, PDSO24
BQ3285S 1 TIMER(S), REAL TIME CLOCK, PDSO24
BQ3387P 1 TIMER(S), REAL TIME CLOCK, PDIP24
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