參數(shù)資料
型號(hào): BQ3285LDSSTRG4
廠商: TEXAS INSTRUMENTS INC
元件分類(lèi): XO, clock
英文描述: REAL TIME CLOCK, PDSO24
封裝: 0.150 INCH, GREEN, PLASTIC, SSOP-24
文件頁(yè)數(shù): 24/27頁(yè)
文件大小: 170K
代理商: BQ3285LDSSTRG4
32kHz Output
The bq3285ED/LD provides for a 32.768kHz output, and
the output is always active whenever VCC is valid (VPFD
+tCSR). The bq3285ED/LD output is not affected by the
bit settings in Register A. Time-keeping aspects, how-
ever, still require setting OS0-OS2.
Interrupts
The bq3285ED/LD allows three individually selected in-
terrupt events to generate an interrupt request. These
three interrupt events are:
n
The periodic interrupt, programmable to occur once
every 122
s to 500ms.
n
The alarm interrupt, programmable to occur once per
second to once per day, is active in battery-backup
mode, providing a “wake-up” feature.
n
The update-ended interrupt, which occurs at the end
of each update cycle.
Each of the three interrupt events is enabled by an indi-
vidual interrupt-enable bit in register B. When an event
occurs, its event flag bit in register C is set. If the corre-
sponding event enable bit is also set, then an interrupt
request is generated.
The interrupt request flag bit
(INTF) of register C is set with every interrupt request.
Reading register C clears all flag bits, including INTF,
and makes INT high-impedance.
Two methods can be used to process bq3285ED/LD in-
terrupt events:
n
Enable interrupt events and use the interrupt
request output to invoke an interrupt service routine.
n
Do not enable the interrupts and use a polling
routine to periodically check the status of the flag
bits.
The individual interrupt sources are described in detail
in the following sections.
6
bq3285ED/LD
Register A Bits
Periodic Interrupt
OSC2
OSC1
OSC0
RS3
RS2
RS1
RS0
Period
Units
0100
0
None
0100
0
1
3.90625
ms
0100
0
1
0
7.8125
ms
0100
0
1
122.070
s
0100
1
0
244.141
s
0100
1
0
1
488.281
s
0100
1
0
976.5625
s
0100
1
1.95315
ms
0101
0
3.90625
ms
0101
0
1
7.8125
ms
0101
0
1
0
15.625
ms
0101
0
1
31.25
ms
0101
1
0
62.5
ms
0101
1
0
1
125
ms
0101
1
0
250
ms
0101
1
500
ms
011
X
same as above defined
by RS3–RS0
Table 3. Periodic Interrupt Rate
July 1997
相關(guān)PDF資料
PDF描述
BQ3285LDSS 0 TIMER(S), REAL TIME CLOCK, PDSO24
BQ3285EDSS 0 TIMER(S), REAL TIME CLOCK, PDSO24
BQ3285LSS 1 TIMER(S), REAL TIME CLOCK, PDSO24
BQ3285S 1 TIMER(S), REAL TIME CLOCK, PDSO24
BQ3387P 1 TIMER(S), REAL TIME CLOCK, PDIP24
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