參數(shù)資料
型號: AX88780
廠商: ASIX Electronics Corporation
英文描述: High-Performance Non-PCI Single-Chip 32-bit 10/100M Fast Ethernet Controller
中文描述: 高性能非PCI單芯片32位10/100M自適應(yīng)快速以太網(wǎng)控制器
文件頁數(shù): 8/49頁
文件大小: 687K
代理商: AX88780
AX88780
2.0 Signal Description
2.1 Signal Type Definition
I3:
I2:
O3:
O2:
IO3:
TSO:
OD:
PD:
PU:
GND:
GNDA:
GNDR:
VCC3:
VCC3R:
VCC2:
VCC2A:
I:
O:
IO:
Input, 3.3V with 5V tolerance
Input, 2.5V with 3.3V tolerance
Output, 3.3V
Output, 2.5V
Input/Output, input 3.3V with 5V tolerance
Tri-State Output
Open Drain allows multiple devices to share as a wire-OR
Internal 75K Pull Down
Internal 75K Pull Up
Digital Ground
Analog Ground
Ground for Regulator
3.3V power
3.3V for regulator
2.5V power
2.5V for analog
Input only
Output only
Input/Output
2.2 Host Interface
Table 1 : Host Interface signals group
Pin Name
INTN
Type
TSO, 8mA
Pin NO
102
Pin Description
Interrupt to host system
When the polarity is active high, this signal must be pulled low, otherwise pulled
high in active low environment. Software set the bit6 of command register (CMD) to
response the polarity.
Reset signal: active low.
System Clock. The reference frequency is from 40MHz to 100MHz
Wake-up signal to system. When the polarity is active high, this signal must be
pulled low, otherwise pulled high in active low environment. Software set the bit0 of
command register (CMD) to response the polarity.
Data bus bit0.
Data bus bit1.
Data bus bit2.
Data bus bit3.
Data bus bit4.
Data bus bit5.
Data bus bit6.
Data bus bit7.
Data bus bit8.
Data bus bit9.
Data bus bit10.
Data bus bit11.
Data bus bit12.
Data bus bit13.
Data bus bit14.
Data bus bit15.
Data bus bit16, internal pull low.
RST_N
HCLK
WAKEUP
I3
I3
TSO, 8mA
103
104
115
HD0
HD1
HD2
HD3
HD4
HD5
HD6
HD7
HD8
HD9
HD10
HD11
HD12
HD13
HD14
HD15
HD16
IO3, 8mA
IO3, 8mA
IO3, 8mA
IO3, 8mA
IO3, 8mA
IO3, 8mA
IO3, 8mA
IO3, 8mA
IO3, 8mA
IO3, 8mA
IO3, 8mA
IO3, 8mA
IO3, 8mA
IO3, 8mA
IO3, 8mA
IO3, 8mA
IO3, 8mA
19
18
17
16
15
14
12
11
10
9
7
6
5
3
2
128
127
8
ASIX ELECTRONICS CORPORATION
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