- 您現在的位置：買賣IC網 > PDF目錄375384 > AX88780 (ASIX Electronics Corporation) High-Performance Non-PCI Single-Chip 32-bit 10/100M Fast Ethernet Controller PDF資料下載
參數資料
| 型號： | AX88780 |
| 廠商： | ASIX Electronics Corporation |
| 英文描述： | High-Performance Non-PCI Single-Chip 32-bit 10/100M Fast Ethernet Controller |
| 中文描述： | 高性能非PCI單芯片32位10/100M自適應快速以太網控制器 |
| 文件頁數： | 27/49頁 |
| 文件大?。?/td> | 687K |
| 代理商： | AX88780 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁當前第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁
AX88780
4.28 RXFILTER--RX Packet Filter Register
Offset Address = FC80h Default = 32’h0000_002C
Field
Name
Type
31:6
-
R
-
R/W
4
MULTI_HASH
R/W
Default
All 0’s
1
0
Description
Reserved
Reserved
Receive Multicast packet by
lookup hash table
.
When this is enabled, AX88780 will receive multicast packet by the
hash mapping function. It will refer to HASTAB0, HASHTAB1,
HASHTAB2 and HASHTAB3 to look up the table.
1 = enable
0 = disable
Receive Broadcast packet
When this bit is enabled, AX88780 will receive the broadcast packet
1 = enable
0 = disable
Receive Directed Packet.
If this bit is enabled, AX88780 will compare the destination address
field of received packet with the address of MAC (refer to MACID0,
MACID1, MACID2). When it is matched and good CRC, the packet
will be passed to driver. Otherwise it will be dropped.
1 = enable
0 = disable
Receive all Multicast Packets.
If this bit is enabled, any multicast packet (good CRC) will be received
and passed to driver.
1 = enable
0 = disable
Receive Anything.
If this bit is enabled, any packet whether it is good or fail will be
received and passed to driver.
1 = enable
0 = disable
3
BROADCAST
R/W
1
2
UNICAST
R/W
1
1
MULTICAST
R/W
0
0
RXANY
R/W
0
5
4.29 MDIOCTRL--MDIO Control Register
Offset Address = FC84h Default = 32’h0000_0000
Field
Name
Type
Default
31:16
-
R
All 0’s
15
WTEN
R/W
0
Description
Reserved
Write Enable.
Driver enables this bit to issue a write cycle to PHY, it will be cleared when
finished the write cycle
1 = enable
0 = disable
Read Enable.
Driver enables this bit to issue a read cycle to PHY. This bit will be cleared
when finished the read cycle
1 = enable
0 = disable
5’b00000 PHY Register Index
If driver wants to access PHY, set this field to define the internal register
index of PHY.
14
RDEN
R/W
0
12:8
PHYCRIDX R/W
27
ASIX ELECTRONICS CORPORATION
相關PDF資料 |
PDF描述 |
|---|---|
| AX88790L | 10/100BASE 3-in-1 PCMCIA Fast Ethernet Controller |
| AX88796BLF | IC,MC14411P |
| AX88796BLI | Low-pin-count Non-PCI 8/16-bit 10/100M Fast Ethernet Controller |
| AX88872P | 10/100BASE Dual Speed “Swipeater” Controller |
| AX9902MS | 2N and 2P-Channel Enhancement Mode Power MOSFET |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AX88780_07 | 制造商:ASIX 制造商全稱:ASIX 功能描述:High-Performance Non-PCI Single-Chip 32-bit 10/100M Fast Ethernet Controller |
| AX88782 | 制造商:ASIX 制造商全稱:ASIX 功能描述:ASIX Multi-Port Ethernet Controller |
| AX88783 | 制造商:ASIX 制造商全稱:ASIX 功能描述:ASIX Multi-Port Ethernet Controller |
| AX88790L | 制造商:ASIX 制造商全稱:ASIX 功能描述:10/100BASE 3-in-1 PCMCIA Fast Ethernet Controller |
| AX88796 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:3-in-1 Local Bus Fast Ethernet Controller |
發(fā)布緊急采購，3分鐘左右您將得到回復。